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/linux/drivers/pci/controller/dwc/
H A DKconfig3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
51 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
55 bool "Axis ARTPEC-6 PCIe controller (endpoint mode)"
61 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
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H A Dpcie-visconti.c3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
96 /* Access registers in PCIe ulreg */
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
107 /* Access registers in PCIe smu */
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
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H A Dpcie-uniphier.c3 * PCIe host controller driver for UniPhier SoCs
23 #include "pcie-designware.h"
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
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H A Dpcie-keembay.c3 * PCIe controller driver for Intel Keem Bay
22 #include "pcie-designware.h"
72 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument
74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
78 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument
88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
92 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
106 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_link_up() local
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H A Dpcie-armada8k.c3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
25 #include "pcie-designware.h"
73 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
78 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
79 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
83 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
89 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
93 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
94 pcie->phy_count); in armada8k_pcie_enable_phys()
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H A Dpci-layerscape-ep.c3 * PCIe controller EP driver for Freescale Layerscape SoCs
19 #include "pcie-designware.h"
24 /* PEX PFa PCIE PME and message interrupt registers*/
52 static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset) in ls_pcie_pf_lut_readl() argument
54 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_readl()
56 if (pcie->big_endian) in ls_pcie_pf_lut_readl()
62 static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value) in ls_pcie_pf_lut_writel() argument
64 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_writel()
66 if (pcie->big_endian) in ls_pcie_pf_lut_writel()
74 struct ls_pcie_ep *pcie = dev_id; in ls_pcie_ep_event_handler() local
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H A DMakefile2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
9 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
11 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
15 obj-$(CONFIG_PCIE_QCOM_COMMON) += pcie-qcom-common.o
16 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
17 obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o
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H A Dpcie-al.c3 * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
26 struct al_pcie_acpi *pcie = cfg->priv; in al_pcie_map_bus() local
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus()
31 * The DW PCIe core doesn't filter out transactions to other in al_pcie_map_bus()
92 #include "pcie-designware.h"
132 void __iomem *controller_base; /* base of PCIe unit (not DW core) */
142 static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset) in al_pcie_controller_readl() argument
144 return readl_relaxed(pcie->controller_base + offset); in al_pcie_controller_readl()
147 static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset, in al_pcie_controller_writel() argument
150 writel_relaxed(val, pcie->controller_base + offset); in al_pcie_controller_writel()
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c3 * PCIe host controller driver for Mobiveil PCIe Host controller
25 #include "pcie-mobiveil.h"
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
71 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
85 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
86 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
87 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
102 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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H A Dpcie-mobiveil.c3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
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H A Dpcie-layerscape-gen4.c3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
23 #include "pcie-mobiveil.h"
45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); in ls_g4_pcie_link_up()
70 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_disable_interrupt() argument
72 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_disable_interrupt()
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/linux/drivers/pci/controller/
H A Dpcie-xilinx.c3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
7 * Based on the Tegra PCIe driver
94 * struct xilinx_pcie - PCIe port information
113 static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg) in pcie_read() argument
115 return readl(pcie->reg_base + reg); in pcie_read()
118 static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg) in pcie_write() argument
120 writel(val, pcie->reg_base + reg); in pcie_write()
123 static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie) in xilinx_pcie_link_up() argument
125 return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) & in xilinx_pcie_link_up()
131 * @pcie: PCIe port information
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H A Dpcie-iproc.c24 #include "pcie-iproc.h"
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
229 * iProc PCIe host registers
306 /* iProc PCIe PAXB BCMA registers */
317 /* iProc PCIe PAXB registers */
333 /* iProc PCIe PAXB v2 registers */
364 /* iProc PCIe PAXC v1 registers */
373 /* iProc PCIe PAXC v2 registers */
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H A DKconfig7 tristate "Aardvark PCIe controller"
13 Add support for Aardvark 64bit PCIe Host Controller. This
18 tristate "Altera PCIe controller"
21 Say Y here if you want to enable PCIe controller support on Altera
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
38 tristate "Apple PCIe controller"
44 Say Y here if you want to enable PCIe controller support on Apple
55 tristate "Broadcom Brcmstb PCIe controller"
62 Say Y here to enable PCIe host controller support for
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H A Dpcie-rcar.c3 * PCIe driver for Renesas R-Car SoCs
12 #include "pcie-rcar.h"
14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
31 rcar_pci_write_reg(pcie, val, where & ~3); in rcar_rmw32()
34 int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) in rcar_pcie_wait_for_phyrdy() argument
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H A Dpcie-iproc-bcma.c15 #include "pcie-iproc.h"
28 struct iproc_pcie *pcie = dev->sysdata; in iproc_bcma_pcie_map_irq() local
29 struct bcma_device *bdev = container_of(pcie->dev, struct bcma_device, dev); in iproc_bcma_pcie_map_irq()
37 struct iproc_pcie *pcie; in iproc_bcma_pcie_probe() local
41 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_bcma_pcie_probe()
45 pcie = pci_host_bridge_priv(bridge); in iproc_bcma_pcie_probe()
47 pcie->dev = dev; in iproc_bcma_pcie_probe()
49 pcie->type = IPROC_PCIE_PAXB_BCMA; in iproc_bcma_pcie_probe()
50 pcie->base = bdev->io_addr; in iproc_bcma_pcie_probe()
51 if (!pcie->base) { in iproc_bcma_pcie_probe()
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H A DMakefile11 obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
12 obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
17 obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
18 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
19 obj-$(CONFIG_PCIE_XILINX_CPM) += pcie-xilinx-cpm.o
20 obj-$(CONFIG_PCIE_XILINX_DMA_PL) += pcie-xilinx-dma-pl.o
25 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
26 obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
27 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
28 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
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/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-host.c3 // Cadence PCIe host controller driver.
13 #include "pcie-cadence.h"
33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
52 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()
58 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0); in cdns_pci_map_bus()
71 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0); in cdns_pci_map_bus()
82 static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) in cdns_pcie_host_training_complete() argument
91 lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); in cdns_pcie_host_training_complete()
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H A Dpcie-cadence.h3 // Cadence PCIe controller driver.
150 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
163 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
167 /* Region r Outbound PCIe Descriptor Register 0 */
183 /* Region r Outbound PCIe Descriptor Register 1 */
201 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */
236 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
285 int (*start_link)(struct cdns_pcie *pcie);
286 void (*stop_link)(struct cdns_pcie *pcie);
287 bool (*link_up)(struct cdns_pcie *pcie);
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H A Dpcie-cadence-plat.c3 * Cadence PCIe platform driver.
13 #include "pcie-cadence.h"
18 * struct cdns_plat_pcie - private data for this PCIe platform driver
19 * @pcie: Cadence PCIe controller
22 struct cdns_pcie *pcie; member
31 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument
73 rc->pcie.dev = dev; in cdns_plat_pcie_probe()
74 rc->pcie.ops = &cdns_plat_ops; in cdns_plat_pcie_probe()
75 cdns_plat_pcie->pcie = &rc->pcie; in cdns_plat_pcie_probe()
77 ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); in cdns_plat_pcie_probe()
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/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ep.yaml4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
7 title: Qualcomm PCIe Endpoint Controller
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
20 - const: qcom,sdx65-pcie-ep
21 - const: qcom,sdx55-pcie-ep
27 - description: DesignWare PCIe registers
67 - description: PCIe Global interrupt
68 - description: PCIe Doorbell interrupt
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H A Dfsl,layerscape-pcie.yaml4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
7 title: Freescale Layerscape PCIe Root Complex(RC) controller
13 This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
19 register available in the Freescale PCIe controller register set,
20 which can allow determining the underlying DesignWare PCIe controller version
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
30 - fsl,ls1043a-pcie
31 - fsl,ls1046a-pcie
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H A Dti,j721e-pci-ep.yaml8 title: TI J721E PCI EP (PCIe Wrapper)
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
20 - const: ti,am64-pcie-ep
21 - const: ti,j721e-pcie-ep
22 - description: PCIe EP controller in J7200
24 - const: ti,j7200-pcie-ep
25 - const: ti,j721e-pcie-ep
37 ti,syscon-pcie-ctrl:
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H A Dmvebu-pci.txt1 * Marvell EBU PCIe interfaces
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
15 - ranges: ranges describing the MMIO registers to control the PCIe
17 the memory and I/O regions of each PCIe interface.
28 registers of this PCIe interface, from the base of the internal
46 * s is the PCI slot that corresponds to this PCIe interface
58 PCIe interface, having the following mandatory properties:
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H A Dnvidia,tegra20-pcie.txt1 NVIDIA Tegra PCIe controller
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
11 contain BPMP phandle and PCIe power partition ID. This is required only
71 - "default": active state, puts PCIe I/O out of deep power down state
72 - "idle": puts PCIe I/O into deep power down state
79 - pcie
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