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/linux/drivers/clk/
H A Dclk-multiplier.c15 static inline u32 clk_mult_readl(struct clk_multiplier *mult) in clk_mult_readl() argument
17 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_readl()
18 return ioread32be(mult->reg); in clk_mult_readl()
20 return readl(mult->reg); in clk_mult_readl()
23 static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) in clk_mult_writel() argument
25 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_writel()
26 iowrite32be(val, mult->reg); in clk_mult_writel()
28 writel(val, mult->reg); in clk_mult_writel()
31 static unsigned long __get_mult(struct clk_multiplier *mult, in __get_mult() argument
35 if (mult->flags & CLK_MULTIPLIER_ROUND_CLOSEST) in __get_mult()
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H A Dclk-fixed-factor.c18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
41 best_parent = (req->rate / fix->mult) * fix->div; in clk_factor_determine_rate()
45 req->rate = (req->best_parent_rate / fix->div) * fix->mult; in clk_factor_determine_rate()
97 unsigned long flags, unsigned int mult, unsigned int div, in __clk_hw_register_fixed_factor() argument
118 fix->mult = mult; in __clk_hw_register_fixed_factor()
159 * @mult: multiplier
167 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_index() argument
172 flags, mult, div, 0, 0, true); in devm_clk_hw_register_fixed_factor_index()
183 * @mult: multiplier
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/linux/drivers/clk/imx/
H A Dclk-pllv4.c50 /* Valid PLL MULT Table */
53 /* Valid PLL MULT range, (max, min) */
82 u32 mult, mfn, mfd; in clk_pllv4_recalc_rate() local
85 mult = readl_relaxed(pll->base + pll->cfg_offset); in clk_pllv4_recalc_rate()
86 mult &= BM_PLL_MULT; in clk_pllv4_recalc_rate()
87 mult >>= BP_PLL_MULT; in clk_pllv4_recalc_rate()
95 return (parent_rate * mult) + (u32)temp64; in clk_pllv4_recalc_rate()
107 u32 mult; in clk_pllv4_determine_rate() local
112 mult = temp64; in clk_pllv4_determine_rate()
113 if (mult >= pllv4_mult_range[1] && in clk_pllv4_determine_rate()
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/linux/drivers/clk/renesas/
H A Drcar-gen3-cpg.c37 #define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */
56 unsigned int mult; in cpg_pll_clk_recalc_rate() local
58 mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1; in cpg_pll_clk_recalc_rate()
60 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
67 unsigned int min_mult, max_mult, mult; in cpg_pll_clk_determine_rate() local
76 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
77 mult = clamp(mult, min_mult, max_mult); in cpg_pll_clk_determine_rate()
79 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
87 unsigned int mult, i; in cpg_pll_clk_set_rate() local
90 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); in cpg_pll_clk_set_rate()
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H A Drcar-gen2-cpg.c41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
57 unsigned int mult; in cpg_z_clk_recalc_rate() local
61 mult = 32 - val; in cpg_z_clk_recalc_rate()
63 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
70 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
77 mult = div64_ul(req->rate * 32ULL, prate); in cpg_z_clk_determine_rate()
78 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
80 req->rate = div_u64((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
88 unsigned int mult; in cpg_z_clk_set_rate() local
92 mult = div64_ul(rate * 32ULL, parent_rate); in cpg_z_clk_set_rate()
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H A Drcar-gen4-cpg.c56 #define CPG_PLLxCR0_NI8 GENMASK(27, 20) /* Integer mult. factor */
57 #define CPG_PLLxCR1_NF25 GENMASK(24, 0) /* Fractional mult. factor */
60 #define CPG_PLLxCR0_NI9 GENMASK(28, 20) /* Integer mult. factor */
61 #define CPG_PLLxCR1_NF24 GENMASK(23, 0) /* Fractional mult. factor */
282 unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); in cpg_z_clk_recalc_rate() local
284 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, in cpg_z_clk_recalc_rate()
292 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
312 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); in cpg_z_clk_determine_rate()
313 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
315 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
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H A Dclk-sh73a0.c78 unsigned int mult = 1; in sh73a0_cpg_register_clock() local
109 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
113 mult *= 2; in sh73a0_cpg_register_clock()
121 mult = readl(dsi_reg); in sh73a0_cpg_register_clock()
122 if (!(mult & 0x8000)) in sh73a0_cpg_register_clock()
123 mult = 1; in sh73a0_cpg_register_clock()
125 mult = (mult & 0x3f) + 1; in sh73a0_cpg_register_clock()
151 mult, div); in sh73a0_cpg_register_clock()
/linux/drivers/clk/sunxi/
H A Dclk-sun4i-pll3.c24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local
48 mult = kzalloc_obj(*mult); in sun4i_a10_pll3_setup()
49 if (!mult) in sun4i_a10_pll3_setup()
52 mult->reg = reg; in sun4i_a10_pll3_setup()
53 mult->shift = SUN4I_A10_PLL3_DIV_SHIFT; in sun4i_a10_pll3_setup()
54 mult->width = SUN4I_A10_PLL3_DIV_WIDTH; in sun4i_a10_pll3_setup()
55 mult->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
60 &mult->hw, &clk_multiplier_ops, in sun4i_a10_pll3_setup()
80 kfree(mult); in sun4i_a10_pll3_setup()
H A Dclk-a10-pll2.c44 struct clk_multiplier *mult; in sun4i_pll2_setup() local
83 mult = kzalloc_obj(struct clk_multiplier); in sun4i_pll2_setup()
84 if (!mult) in sun4i_pll2_setup()
87 mult->reg = reg; in sun4i_pll2_setup()
88 mult->shift = SUN4I_PLL2_N_SHIFT; in sun4i_pll2_setup()
89 mult->width = 7; in sun4i_pll2_setup()
90 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | in sun4i_pll2_setup()
92 mult->lock = &sun4i_a10_pll2_lock; in sun4i_pll2_setup()
98 &mult->hw, &clk_multiplier_ops, in sun4i_pll2_setup()
168 kfree(mult); in sun4i_pll2_setup()
/linux/drivers/clk/mvebu/
H A Dorion.c60 int *mult, int *div) in mv88f5181_get_clk_ratio() argument
65 *mult = 1; in mv88f5181_get_clk_ratio()
68 *mult = 1; in mv88f5181_get_clk_ratio()
71 *mult = 0; in mv88f5181_get_clk_ratio()
128 int *mult, int *div) in mv88f5182_get_clk_ratio() argument
133 *mult = 1; in mv88f5182_get_clk_ratio()
136 *mult = 1; in mv88f5182_get_clk_ratio()
139 *mult = 0; in mv88f5182_get_clk_ratio()
185 int *mult, int *div) in mv88f5281_get_clk_ratio() argument
190 *mult = 1; in mv88f5281_get_clk_ratio()
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/linux/drivers/iio/common/inv_sensors/
H A Dinv_sensors_timestamp.c52 ts->mult = chip->init_period / chip->clock_period; in inv_sensors_timestamp_init()
63 uint32_t mult; in inv_sensors_timestamp_update_odr() local
69 mult = period / ts->chip.clock_period; in inv_sensors_timestamp_update_odr()
70 if (mult != ts->mult) in inv_sensors_timestamp_update_odr()
71 ts->new_mult = mult; in inv_sensors_timestamp_update_odr()
86 period_min = ts->min_period * ts->mult; in inv_validate_period()
87 period_max = ts->max_period * ts->mult; in inv_validate_period()
103 new_chip_period = period / ts->mult; in inv_update_chip_period()
105 ts->period = ts->mult * ts->chip_period.val; in inv_update_chip_period()
112 const int64_t period_min = (int64_t)ts->min_period * ts->mult; in inv_align_timestamp_it()
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/linux/sound/core/
H A Dpcm_timer.c21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local
24 mult = 1000000000; in snd_pcm_timer_resolution_change()
28 l = gcd(mult, rate); in snd_pcm_timer_resolution_change()
29 mult /= l; in snd_pcm_timer_resolution_change()
38 while ((mult * fsize) / fsize != mult) { in snd_pcm_timer_resolution_change()
39 mult /= 2; in snd_pcm_timer_resolution_change()
49 runtime->timer_resolution = (mult * fsize / rate) * post; in snd_pcm_timer_resolution_change()
/linux/include/linux/
H A Drandom.h78 u32 mult = ceil * get_random_u8(); in get_random_u32_below() local
79 if (likely(is_power_of_2(ceil) || (u8)mult >= (1U << 8) % ceil)) in get_random_u32_below()
80 return mult >> 8; in get_random_u32_below()
82 u32 mult = ceil * get_random_u16(); in get_random_u32_below() local
83 if (likely(is_power_of_2(ceil) || (u16)mult >= (1U << 16) % ceil)) in get_random_u32_below()
84 return mult >> 16; in get_random_u32_below()
86 u64 mult = (u64)ceil * get_random_u32(); in get_random_u32_below() local
87 if (likely(is_power_of_2(ceil) || (u32)mult >= -ceil % ceil)) in get_random_u32_below()
88 return mult >> 32; in get_random_u32_below()
/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-omap3430es2plus-clocks.dtsi51 clock-mult = <1>;
83 clock-mult = <1>;
107 clock-mult = <1>;
115 clock-mult = <1>;
123 clock-mult = <1>;
131 clock-mult = <1>;
139 clock-mult = <1>;
147 clock-mult = <1>;
155 clock-mult = <1>;
163 clock-mult = <1>;
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H A Dam33xx-clocks.dtsi22 clock-mult = <1>;
31 clock-mult = <1>;
40 clock-mult = <1>;
49 clock-mult = <1>;
58 clock-mult = <1>;
67 clock-mult = <1>;
76 clock-mult = <1>;
85 clock-mult = <1>;
94 clock-mult = <1>;
103 clock-mult = <1>;
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H A Dam43xx-clocks.dtsi40 clock-mult = <1>;
49 clock-mult = <1>;
58 clock-mult = <1>;
67 clock-mult = <1>;
76 clock-mult = <1>;
85 clock-mult = <1>;
94 clock-mult = <1>;
103 clock-mult = <1>;
112 clock-mult = <1>;
121 clock-mult = <1>;
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/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpllcore.c113 u32 cur_rate, low, mult, div, valid_rate, done_rate; in omap2_reprogram_dpllcore() local
119 mult = omap2xxx_cm_get_core_clk_src(); in omap2_reprogram_dpllcore()
121 if ((rate == (cur_rate / 2)) && (mult == 2)) { in omap2_reprogram_dpllcore()
123 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { in omap2_reprogram_dpllcore()
130 if (mult == 1) in omap2_reprogram_dpllcore()
148 mult = ((rate / 2) / 1000000); in omap2_reprogram_dpllcore()
152 mult = (rate / 1000000); in omap2_reprogram_dpllcore()
156 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); in omap2_reprogram_dpllcore()
/linux/drivers/clk/ti/
H A Dfixed-factor.c33 u32 div, mult; in of_ti_fixed_factor_clk_setup() local
41 if (of_property_read_u32(node, "ti,clock-mult", &mult)) { in of_ti_fixed_factor_clk_setup()
42 pr_err("%pOFn must have a clock-mult property\n", node); in of_ti_fixed_factor_clk_setup()
52 mult, div); in of_ti_fixed_factor_clk_setup()
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi28 clock-mult = <1>;
37 clock-mult = <1>;
66 clock-mult = <1>;
75 clock-mult = <1>;
84 clock-mult = <1>;
93 clock-mult = <1>;
102 clock-mult = <1>;
111 clock-mult = <1>;
120 clock-mult = <1>;
129 clock-mult = <1>;
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/linux/drivers/clk/x86/
H A Dclk-cgu-pll.c22 * rate = (prate * mult + (prate * frac) / frac_div) / div
25 lgm_pll_calc_rate(unsigned long prate, unsigned int mult, in lgm_pll_calc_rate() argument
31 crate = rate64 * mult; in lgm_pll_calc_rate()
43 unsigned int div, mult, frac; in lgm_pll_recalc_rate() local
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
52 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); in lgm_pll_recalc_rate()
/linux/drivers/clk/davinci/
H A Dpll.c118 u32 mult; in davinci_pll_recalc_rate() local
120 mult = readl(pll->base + PLLM) & pll->pllm_mask; in davinci_pll_recalc_rate()
121 rate *= mult + 1; in davinci_pll_recalc_rate()
134 u32 mult; in davinci_pll_determine_rate() local
141 mult = rate / parent_rate; in davinci_pll_determine_rate()
142 best_rate = parent_rate * mult; in davinci_pll_determine_rate()
149 if (mult < pll->pllm_min || mult > pll->pllm_max) in davinci_pll_determine_rate()
160 for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { in davinci_pll_determine_rate()
161 parent_rate = clk_hw_round_rate(parent, rate / mult); in davinci_pll_determine_rate()
162 r = parent_rate * mult; in davinci_pll_determine_rate()
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/linux/sound/soc/codecs/
H A Des8311.c328 unsigned int mult; member
383 unsigned int mult = coeff->mult; in es8311_cmp_adj_mclk_coeff() local
394 mult = coeff->mclk / mclk_freq; in es8311_cmp_adj_mclk_coeff()
395 if (mult == 2 || mult == 4 || mult == 8) { in es8311_cmp_adj_mclk_coeff()
396 mult *= coeff->mult; in es8311_cmp_adj_mclk_coeff()
397 if (mult <= 8) in es8311_cmp_adj_mclk_coeff()
406 out_coeff->mult = mult; in es8311_cmp_adj_mclk_coeff()
562 unsigned int mult; in es8311_hw_params() local
564 switch (coeff.mult) { in es8311_hw_params()
566 mult = 0; in es8311_hw_params()
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/linux/drivers/net/can/rockchip/
H A Drockchip_canfd-timestamp.c69 clocks_calc_mult_shift(&cc->mult, &cc->shift, rate, NSEC_PER_SEC, in rkcanfd_timestamp_init()
72 max_cycles = div_u64(ULLONG_MAX, cc->mult); in rkcanfd_timestamp_init()
74 work_delay_ns = clocksource_cyc2ns(max_cycles, cc->mult, cc->shift); in rkcanfd_timestamp_init()
78 …netdev_dbg(priv->ndev, "clock=%lu.%02luMHz bitrate=%lu.%02luMBit/s div=%u rate=%lu.%02luMHz mult=%… in rkcanfd_timestamp_init()
86 cc->mult, cc->shift, in rkcanfd_timestamp_init()
/linux/kernel/time/
H A Dclockevents.c38 if (WARN_ON(!evt->mult)) in cev_delta2ns()
39 evt->mult = 1; in cev_delta2ns()
40 rnd = (u64) evt->mult - 1; in cev_delta2ns()
52 * For mult <= (1 << shift) we can safely add mult - 1 to in cev_delta2ns()
56 * For mult > (1 << shift), i.e. device frequency is > 1GHz we in cev_delta2ns()
57 * need to be careful. Adding mult - 1 will result in a value in cev_delta2ns()
59 * than latch by up to (mult - 1) >> shift. For the min_delta in cev_delta2ns()
69 (!ismax || evt->mult <= (1ULL << evt->shift))) in cev_delta2ns()
72 do_div(clc, evt->mult); in cev_delta2ns()
164 if (WARN_ON(!dev->mult)) in clockevents_switch_state()
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H A Dtimekeeping.c122 * returns nanoseconds already so no conversion is required, hence mult=1
130 .mult = 1, \
349 /* Do the ns -> cycle conversion first, using original mult */ in tk_setup_internals()
353 tmp += clock->mult/2; in tk_setup_internals()
354 do_div(tmp, clock->mult); in tk_setup_internals()
362 tk->xtime_interval = interval * clock->mult; in tk_setup_internals()
364 tk->raw_interval = interval * clock->mult; in tk_setup_internals()
386 * The timekeeper keeps its own mult values for the currently in tk_setup_internals()
390 tk->tkr_mono.mult = clock->mult; in tk_setup_internals()
391 tk->tkr_raw.mult = clock->mult; in tk_setup_internals()
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