| /linux/drivers/clk/ |
| H A D | clk-multiplier.c | 15 static inline u32 clk_mult_readl(struct clk_multiplier *mult) in clk_mult_readl() argument
17 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_readl()
18 return ioread32be(mult->reg); in clk_mult_readl()
20 return readl(mult->reg); in clk_mult_readl()
23 static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) in clk_mult_writel() argument
25 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_writel()
26 iowrite32be(val, mult->reg); in clk_mult_writel()
28 writel(val, mult->reg); in clk_mult_writel()
31 static unsigned long __get_mult(struct clk_multiplier *mult, in __get_mult() argument
35 if (mult->flags & CLK_MULTIPLIER_ROUND_CLOSEST) in __get_mult()
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| H A D | clk-fixed-factor.c | 18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
41 best_parent = (req->rate / fix->mult) * fix->div; in clk_factor_determine_rate()
45 req->rate = (req->best_parent_rate / fix->div) * fix->mult; in clk_factor_determine_rate()
97 unsigned long flags, unsigned int mult, unsigned int div, in __clk_hw_register_fixed_factor() argument
118 fix->mult = mult; in __clk_hw_register_fixed_factor()
159 * @mult: multiplier
167 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_index() argument
172 flags, mult, div, 0, 0, true); in devm_clk_hw_register_fixed_factor_index()
183 * @mult: multiplier
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| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_mult.c | 14 unsigned long mult, min, max; member
18 struct _ccu_mult *mult) in ccu_mult_find_best() argument
23 if (_mult < mult->min) in ccu_mult_find_best()
24 _mult = mult->min; in ccu_mult_find_best()
26 if (_mult > mult->max) in ccu_mult_find_best()
27 _mult = mult->max; in ccu_mult_find_best()
29 mult->mult = _mult; in ccu_mult_find_best()
41 _cm.min = cm->mult.min; in ccu_mult_round_rate()
43 if (cm->mult.max) in ccu_mult_round_rate()
44 _cm.max = cm->mult.max; in ccu_mult_round_rate()
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| /linux/drivers/clk/sunxi/ |
| H A D | clk-sun4i-pll3.c | 24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local
48 mult = kzalloc(sizeof(*mult), GFP_KERNEL); in sun4i_a10_pll3_setup()
49 if (!mult) in sun4i_a10_pll3_setup()
52 mult->reg = reg; in sun4i_a10_pll3_setup()
53 mult->shift = SUN4I_A10_PLL3_DIV_SHIFT; in sun4i_a10_pll3_setup()
54 mult->width = SUN4I_A10_PLL3_DIV_WIDTH; in sun4i_a10_pll3_setup()
55 mult->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
60 &mult->hw, &clk_multiplier_ops, in sun4i_a10_pll3_setup()
80 kfree(mult); in sun4i_a10_pll3_setup()
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| H A D | clk-a10-pll2.c | 44 struct clk_multiplier *mult; in sun4i_pll2_setup() local
83 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); in sun4i_pll2_setup()
84 if (!mult) in sun4i_pll2_setup()
87 mult->reg = reg; in sun4i_pll2_setup()
88 mult->shift = SUN4I_PLL2_N_SHIFT; in sun4i_pll2_setup()
89 mult->width = 7; in sun4i_pll2_setup()
90 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | in sun4i_pll2_setup()
92 mult->lock = &sun4i_a10_pll2_lock; in sun4i_pll2_setup()
98 &mult->hw, &clk_multiplier_ops, in sun4i_pll2_setup()
168 kfree(mult); in sun4i_pll2_setup()
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| /linux/drivers/clk/mvebu/ |
| H A D | orion.c | 60 int *mult, int *div) in mv88f5181_get_clk_ratio() argument
65 *mult = 1; in mv88f5181_get_clk_ratio()
68 *mult = 1; in mv88f5181_get_clk_ratio()
71 *mult = 0; in mv88f5181_get_clk_ratio()
128 int *mult, int *div) in mv88f5182_get_clk_ratio() argument
133 *mult = 1; in mv88f5182_get_clk_ratio()
136 *mult = 1; in mv88f5182_get_clk_ratio()
139 *mult = 0; in mv88f5182_get_clk_ratio()
185 int *mult, int *div) in mv88f5281_get_clk_ratio() argument
190 *mult = 1; in mv88f5281_get_clk_ratio()
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| /linux/drivers/iio/common/inv_sensors/ |
| H A D | inv_sensors_timestamp.c | 52 ts->mult = chip->init_period / chip->clock_period; in inv_sensors_timestamp_init()
63 uint32_t mult; in inv_sensors_timestamp_update_odr() local
69 mult = period / ts->chip.clock_period; in inv_sensors_timestamp_update_odr()
70 if (mult != ts->mult) in inv_sensors_timestamp_update_odr()
71 ts->new_mult = mult; in inv_sensors_timestamp_update_odr()
86 period_min = ts->min_period * ts->mult; in inv_validate_period()
87 period_max = ts->max_period * ts->mult; in inv_validate_period()
103 new_chip_period = period / ts->mult; in inv_update_chip_period()
105 ts->period = ts->mult * ts->chip_period.val; in inv_update_chip_period()
112 const int64_t period_min = (int64_t)ts->min_period * ts->mult; in inv_align_timestamp_it()
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| /linux/include/linux/ |
| H A D | clocksource.h | 43 * @mult: Cycle to nanosecond multiplier
46 * @maxadj: Maximum adjustment value to mult (~11%)
104 u32 mult; member
158 * mult/2^shift = ns/cyc in clocksource_freq2mult()
159 * mult = ns/cyc * 2^shift in clocksource_freq2mult()
160 * mult = from/freq * 2^shift in clocksource_freq2mult()
161 * mult = from * 2^shift / freq in clocksource_freq2mult()
162 * mult = (from<<shift) / freq in clocksource_freq2mult()
173 * clocksource_khz2mult - calculates mult from khz and shift
186 * clocksource_hz2mult - calculates mult from hz and shift
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| /linux/sound/core/ |
| H A D | pcm_timer.c | 21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local
24 mult = 1000000000; in snd_pcm_timer_resolution_change()
28 l = gcd(mult, rate); in snd_pcm_timer_resolution_change()
29 mult /= l; in snd_pcm_timer_resolution_change()
38 while ((mult * fsize) / fsize != mult) { in snd_pcm_timer_resolution_change()
39 mult /= 2; in snd_pcm_timer_resolution_change()
49 runtime->timer_resolution = (mult * fsize / rate) * post; in snd_pcm_timer_resolution_change()
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap36xx-omap3430es2plus-clocks.dtsi | 51 clock-mult = <1>;
83 clock-mult = <1>;
107 clock-mult = <1>;
115 clock-mult = <1>;
123 clock-mult = <1>;
131 clock-mult = <1>;
139 clock-mult = <1>;
147 clock-mult = <1>;
155 clock-mult = <1>;
163 clock-mult = <1>;
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| H A D | am33xx-clocks.dtsi | 22 clock-mult = <1>;
31 clock-mult = <1>;
40 clock-mult = <1>;
49 clock-mult = <1>;
58 clock-mult = <1>;
67 clock-mult = <1>;
76 clock-mult = <1>;
85 clock-mult = <1>;
94 clock-mult = <1>;
103 clock-mult = <1>;
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| H A D | am43xx-clocks.dtsi | 40 clock-mult = <1>;
49 clock-mult = <1>;
58 clock-mult = <1>;
67 clock-mult = <1>;
76 clock-mult = <1>;
85 clock-mult = <1>;
94 clock-mult = <1>;
103 clock-mult = <1>;
112 clock-mult = <1>;
121 clock-mult = <1>;
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| H A D | omap36xx-clocks.dtsi | 79 clock-mult = <1>;
83 clock-mult = <1>;
87 ti,clock-mult = <1>;
91 ti,clock-mult = <1>;
95 clock-mult = <1>;
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| /linux/drivers/net/ethernet/pensando/ionic/ |
| H A D | ionic_phc.c | 311 ctx->cmd.lif_setphc.mult = cpu_to_le32(phc->cc.mult); in ionic_setphc_cmd()
342 phc->cc.mult = adj; in ionic_phc_adjfine()
524 u64 delay, diff, mult; in ionic_lif_alloc_phc() local
544 phc->cc.mult = le32_to_cpu(ionic->ident.dev.hwstamp_mult); in ionic_lif_alloc_phc()
547 if (!phc->cc.mult) { in ionic_lif_alloc_phc()
550 phc->cc.mult); in ionic_lif_alloc_phc()
556 dev_dbg(lif->ionic->dev, "Device PHC mask %#llx mult %u shift %u\n", in ionic_lif_alloc_phc()
557 phc->cc.mask, phc->cc.mult, phc->cc.shift); in ionic_lif_alloc_phc()
567 diff = U64_MAX / phc->cc.mult / 2; in ionic_lif_alloc_phc()
571 diff = DIV_ROUND_UP(diff, phc->cc.mult); in ionic_lif_alloc_phc()
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| /linux/arch/arm64/boot/dts/broadcom/stingray/ |
| H A D | stingray-clock.dtsi | 46 clock-mult = <1>;
132 clock-mult = <1>;
140 clock-mult = <1>;
149 clock-mult = <1>;
157 clock-mult = <1>;
165 clock-mult = <1>;
173 clock-mult = <1>;
181 clock-mult = <1>;
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| /linux/arch/arm/mach-omap2/ |
| H A D | clkt2xxx_dpllcore.c | 113 u32 cur_rate, low, mult, div, valid_rate, done_rate; in omap2_reprogram_dpllcore() local
119 mult = omap2xxx_cm_get_core_clk_src(); in omap2_reprogram_dpllcore()
121 if ((rate == (cur_rate / 2)) && (mult == 2)) { in omap2_reprogram_dpllcore()
123 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { in omap2_reprogram_dpllcore()
130 if (mult == 1) in omap2_reprogram_dpllcore()
148 mult = ((rate / 2) / 1000000); in omap2_reprogram_dpllcore()
152 mult = (rate / 1000000); in omap2_reprogram_dpllcore()
156 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); in omap2_reprogram_dpllcore()
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| /linux/drivers/clk/renesas/ |
| H A D | clk-sh73a0.c | 78 unsigned int mult = 1; in sh73a0_cpg_register_clock() local
109 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
113 mult *= 2; in sh73a0_cpg_register_clock()
121 mult = readl(dsi_reg); in sh73a0_cpg_register_clock()
122 if (!(mult & 0x8000)) in sh73a0_cpg_register_clock()
123 mult = 1; in sh73a0_cpg_register_clock()
125 mult = (mult & 0x3f) + 1; in sh73a0_cpg_register_clock()
151 mult, div); in sh73a0_cpg_register_clock()
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| /linux/drivers/clk/ti/ |
| H A D | fixed-factor.c | 33 u32 div, mult; in of_ti_fixed_factor_clk_setup() local
41 if (of_property_read_u32(node, "ti,clock-mult", &mult)) { in of_ti_fixed_factor_clk_setup()
42 pr_err("%pOFn must have a clock-mult property\n", node); in of_ti_fixed_factor_clk_setup()
52 mult, div); in of_ti_fixed_factor_clk_setup()
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| /linux/arch/arm/boot/dts/ti/keystone/ |
| H A D | keystone-clocks.dtsi | 28 clock-mult = <1>;
37 clock-mult = <1>;
66 clock-mult = <1>;
75 clock-mult = <1>;
84 clock-mult = <1>;
93 clock-mult = <1>;
102 clock-mult = <1>;
111 clock-mult = <1>;
120 clock-mult = <1>;
129 clock-mult = <1>;
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| /linux/drivers/clk/x86/ |
| H A D | clk-cgu-pll.c | 22 * rate = (prate * mult + (prate * frac) / frac_div) / div
25 lgm_pll_calc_rate(unsigned long prate, unsigned int mult, in lgm_pll_calc_rate() argument
31 crate = rate64 * mult; in lgm_pll_calc_rate()
43 unsigned int div, mult, frac; in lgm_pll_recalc_rate() local
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
52 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); in lgm_pll_recalc_rate()
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| /linux/sound/soc/codecs/ |
| H A D | es8311.c | 328 unsigned int mult; member
383 unsigned int mult = coeff->mult; in es8311_cmp_adj_mclk_coeff() local
394 mult = coeff->mclk / mclk_freq; in es8311_cmp_adj_mclk_coeff()
395 if (mult == 2 || mult == 4 || mult == 8) { in es8311_cmp_adj_mclk_coeff()
396 mult *= coeff->mult; in es8311_cmp_adj_mclk_coeff()
397 if (mult <= 8) in es8311_cmp_adj_mclk_coeff()
406 out_coeff->mult = mult; in es8311_cmp_adj_mclk_coeff()
562 unsigned int mult; in es8311_hw_params() local
564 switch (coeff.mult) { in es8311_hw_params()
566 mult = 0; in es8311_hw_params()
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| /linux/drivers/clk/davinci/ |
| H A D | pll.c | 118 u32 mult; in davinci_pll_recalc_rate() local
120 mult = readl(pll->base + PLLM) & pll->pllm_mask; in davinci_pll_recalc_rate()
121 rate *= mult + 1; in davinci_pll_recalc_rate()
134 u32 mult; in davinci_pll_determine_rate() local
141 mult = rate / parent_rate; in davinci_pll_determine_rate()
142 best_rate = parent_rate * mult; in davinci_pll_determine_rate()
149 if (mult < pll->pllm_min || mult > pll->pllm_max) in davinci_pll_determine_rate()
160 for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { in davinci_pll_determine_rate()
161 parent_rate = clk_hw_round_rate(parent, rate / mult); in davinci_pll_determine_rate()
162 r = parent_rate * mult; in davinci_pll_determine_rate()
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| /linux/kernel/time/ |
| H A D | clocksource.c | 30 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
32 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
36 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
37 * @mult: pointer to mult variable
43 * The function evaluates the shift/mult pair for the scaled math
52 * calculated mult and shift factors. This guarantees that no 64bit
54 * multiplied with the calculated mult factor. Larger ranges may
55 * reduce the conversion accuracy by choosing smaller mult and shift
59 clocks_calc_mult_shift(u32 *mult, u32 *shift, u32 from, u32 to, u32 maxsec) in clocks_calc_mult_shift() argument
75 * Find the conversion shift/mult pair which has the best in clocks_calc_mult_shift()
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| H A D | clockevents.c | 38 if (WARN_ON(!evt->mult)) in cev_delta2ns()
39 evt->mult = 1; in cev_delta2ns()
40 rnd = (u64) evt->mult - 1; in cev_delta2ns()
52 * For mult <= (1 << shift) we can safely add mult - 1 to in cev_delta2ns()
56 * For mult > (1 << shift), i.e. device frequency is > 1GHz we in cev_delta2ns()
57 * need to be careful. Adding mult - 1 will result in a value in cev_delta2ns()
59 * than latch by up to (mult - 1) >> shift. For the min_delta in cev_delta2ns()
69 (!ismax || evt->mult <= (1ULL << evt->shift))) in cev_delta2ns()
72 do_div(clc, evt->mult); in cev_delta2ns()
161 if (WARN_ON(!dev->mult)) in clockevents_switch_state()
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| /linux/drivers/net/can/rockchip/ |
| H A D | rockchip_canfd-timestamp.c | 69 clocks_calc_mult_shift(&cc->mult, &cc->shift, rate, NSEC_PER_SEC, in rkcanfd_timestamp_init()
72 max_cycles = div_u64(ULLONG_MAX, cc->mult); in rkcanfd_timestamp_init()
74 work_delay_ns = clocksource_cyc2ns(max_cycles, cc->mult, cc->shift); in rkcanfd_timestamp_init()
78 …netdev_dbg(priv->ndev, "clock=%lu.%02luMHz bitrate=%lu.%02luMBit/s div=%u rate=%lu.%02luMHz mult=%… in rkcanfd_timestamp_init()
86 cc->mult, cc->shift, in rkcanfd_timestamp_init()
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