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/linux/Documentation/devicetree/bindings/arm/marvell/
H A Darmada-380-mpcore-soc-ctrl.txt1 Marvell Armada 38x CA9 MPcore SoC Controller
6 - compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
9 datasheet for the CA9 MPcore SoC Control registers
11 mpcore-soc-ctrl@20d20 {
12 compatible = "marvell,armada-380-mpcore-soc-ctrl";
/linux/Documentation/devicetree/bindings/arm/
H A Darm,scu.yaml13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
H A Darm,realview.yaml15 earlier CPUs such as TrustZone and multicore (MPCore).
32 - description: ARM RealView Platform Baseboard for ARM 11 MPCore
34 multiprocessing with ARM11 using MPCore using symmetric
/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb-a9mp.dts27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
H A Darm-realview-eb-11mp.dts31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
35 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
H A Darm-realview-eb-mp.dtsi28 * This is the common include file for all MPCore variants of the
30 * and Cortex-A9 MPCore.
H A Darm-realview-eb-a9mp-bbrevd.dts27 model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore";
H A Dvexpress-v2p-ca5s.dts6 * Cortex-A5 MPCore (V2P-CA5s)
H A Dvexpress-v2p-ca15-tc1.dts6 * Cortex-A15 MPCore (V2P-CA15)
H A Dvexpress-v2p-ca9.dts6 * Cortex-A9 MPCore (V2P-CA9)
H A Dvexpress-v2p-ca15_a7.dts6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml252 interrupts = <0 65 0x04>, /* mpcore syncpt */
253 <0 67 0x04>; /* mpcore general */
388 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
389 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts6 * Cortex-A15 MPCore (V2P-CA15)
/linux/Documentation/arch/arm/keystone/
H A Doverview.rst7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm5301x.dtsi12 mpcore-bus@19000000 {
H A Dbcm53573.dtsi35 mpcore@18310000 {
H A Dbcm-hr2.dtsi62 mpcore@19000000 {
H A Dbcm-ns.dtsi49 mpcore-bus@19000000 {
/linux/arch/arm/mach-mvebu/
H A Dpmsu.c79 /* CA9 MPcore SoC Control registers */
443 "marvell,armada-380-mpcore-soc-ctrl"); in armada_38x_cpuidle_init()
/linux/arch/arm/boot/dts/marvell/
H A Darmada-39x.dtsi303 mpcore-soc-ctrl@20d20 {
304 compatible = "marvell,armada-380-mpcore-soc-ctrl";
H A Darmada-38x.dtsi444 mpcore-soc-ctrl@20d20 {
445 compatible = "marvell,armada-380-mpcore-soc-ctrl";
/linux/arch/arm/mm/
H A Dcache-v6.S32 * MPCore.
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml42 The RPU MPCore can operate in split mode (Dual-processor performance), Safety
/linux/arch/arm/
H A DKconfig550 It does not affect the MPCore. This option enables the ARM Ltd.
623 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
727 affecting Cortex-A9 MPCore with two or more processors (all
/linux/arch/arm/kernel/
H A Dhead.S534 teq r3, r4 @ ARM 11MPCore?

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