Home
last modified time | relevance | path

Searched full:level (Results 1 – 25 of 3705) sorted by relevance

12345678910>>...149

/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
57 …DC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This…
21 …rogress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in pr…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
49 …ress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss i…
56 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
63 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
70 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
91 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
[all …]
/linux/lib/zstd/compress/
H A Dclevels.h28 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
29 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
30 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
31 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
32 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, /* level 5 */
33 { 21, 18, 19, 3, 5, 4, ZSTD_lazy }, /* level 6 */
34 { 21, 19, 20, 4, 5, 8, ZSTD_lazy }, /* level 7 */
35 { 21, 19, 20, 4, 5, 16, ZSTD_lazy2 }, /* level 8 */
36 { 22, 20, 21, 4, 5, 16, ZSTD_lazy2 }, /* level 9 */
37 { 22, 21, 22, 5, 5, 16, ZSTD_lazy2 }, /* level 10 */
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This…
21 …rogress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in pr…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
42 …the Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Instruction cach…
49 …ress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss i…
56 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
63 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
70 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
[all …]
/linux/fs/xfs/scrub/
H A Dbtree.c29 int level, in __xchk_btree_process_error() argument
53 trace_xchk_ifork_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
56 trace_xchk_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
67 int level, in xchk_btree_process_error() argument
70 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_process_error()
78 int level, in xchk_btree_xref_process_error() argument
81 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_xref_process_error()
90 int level, in __xchk_btree_set_corrupt() argument
97 trace_xchk_ifork_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
100 trace_xchk_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
[all …]
/linux/arch/sparc/kernel/
H A Dcpumap.c26 /* Increment rover every time level is visited */
34 int level; member
43 int start_index; /* Index of first node of a level in a cpuinfo tree */
44 int end_index; /* Index of last node of a level in a cpuinfo tree */
45 int num_nodes; /* Number of nodes in a level in a cpuinfo tree */
51 /* Offsets into nodes[] for each level of the tree */
52 struct cpuinfo_level level[CPUINFO_LVL_MAX]; member
96 static int cpuinfo_id(int cpu, int level) in cpuinfo_id() argument
100 switch (level) { in cpuinfo_id()
121 * end index, and number of nodes for each level in the cpuinfo tree. The
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
28 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
35 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
49 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
56 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Dcache.json111 …"PublicDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from…
114 …"BriefDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from …
117 …"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a …
120 …"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a p…
123 …"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from t…
126 …"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from th…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t…
150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th…
[all …]
/linux/arch/arm64/kernel/
H A Dcacheinfo.c13 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
24 static inline enum cache_type get_cache_type(int level) in get_cache_type() argument
28 if (level > MAX_CACHE_LEVEL) in get_cache_type()
31 return CLIDR_CTYPE(clidr, level); in get_cache_type()
35 enum cache_type type, unsigned int level) in ci_leaf_init() argument
37 this_leaf->level = level; in ci_leaf_init()
43 unsigned int ctype, level, leaves; in detect_cache_level() local
45 for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { in detect_cache_level()
46 ctype = get_cache_type(level); in detect_cache_level()
48 level--; in detect_cache_level()
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dextended.json7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
21 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
28 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
35 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
42 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
49 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w…
56 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache…
63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in…
70 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dcache.json105 …"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from t…
108 …"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from th…
111 …"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a …
114 …"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a p…
117 …"PublicDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills f…
120 …"BriefDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills fr…
123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
77 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drockchip-pinconf.dtsi23 pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
29 pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
35 pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
41 pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
47 pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
53 pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
59 pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
65 pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
71 pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
77 pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A Dextended.json7 …ption": "A directory write to the Level-1 Data Cache directory where the returned cache line was s…
14 …n": "A directory write to the Level-1 Instruction Cache directory where the returned cache line wa…
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache."
42 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc…
49 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc…
56 … "A directory write to the Level-1 Instruction Cache directory where the returned cache line was s…
63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in…
70 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc…
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
77 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
[all …]
/linux/tools/perf/pmu-events/
H A Dempty-pmu-events.c25 "l1-dcache\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
27 "l1-dcache-load\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
29 "l1-dcache-load-refs\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
31 "l1-dcache-load-reference\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
33 "l1-dcache-load-ops\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
35 "l1-dcache-load-access\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000"
37 "l1-dcache-load-misses\000legacy cache\000Level 1 data cache read misses\000legacy-cache-config=0x10000\000\00000\000\000\000\000\000"
39 "l1-dcache-load-miss\000legacy cache\000Level 1 data cache read misses\000legacy-cache-config=0x10000\000\00010\000\000\000\000\000"
41 "l1-dcache-loads\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00000\000\000\000\000\000"
43 "l1-dcache-loads-refs\000legacy cache\000Level
[all...]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A Dcache.json107 "PublicDescription": "Level 1 data or unified cache demand access",
110 "BriefDescription": "Level 1 data or unified cache demand access"
113 "PublicDescription": "Level 1 data or unified cache preload or prefetch",
116 "BriefDescription": "Level 1 data or unified cache preload or prefetch"
119 "PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
122 "BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
149 "PublicDescription": "Level 1 prefetcher, load prefetch requests generated",
152 "BriefDescription": "Level 1 prefetcher, load prefetch requests generated"
155 "PublicDescription": "Level 1 prefetcher, load prefetch fills into the level
[all...]
/linux/drivers/scsi/
H A Dscsi_logging.h47 #define SCSI_CHECK_LOGGING(SHIFT, BITS, LEVEL, CMD) \ argument
49 if (unlikely((SCSI_LOG_LEVEL(SHIFT, BITS)) > (LEVEL))) \
56 #define SCSI_CHECK_LOGGING(SHIFT, BITS, LEVEL, CMD) do { } while (0) argument
64 #define SCSI_LOG_ERROR_RECOVERY(LEVEL,CMD) \ argument
65 SCSI_CHECK_LOGGING(SCSI_LOG_ERROR_SHIFT, SCSI_LOG_ERROR_BITS, LEVEL,CMD);
66 #define SCSI_LOG_TIMEOUT(LEVEL,CMD) \ argument
67 SCSI_CHECK_LOGGING(SCSI_LOG_TIMEOUT_SHIFT, SCSI_LOG_TIMEOUT_BITS, LEVEL,CMD);
68 #define SCSI_LOG_SCAN_BUS(LEVEL,CMD) \ argument
69 SCSI_CHECK_LOGGING(SCSI_LOG_SCAN_SHIFT, SCSI_LOG_SCAN_BITS, LEVEL,CMD);
70 #define SCSI_LOG_MLQUEUE(LEVEL,CMD) \ argument
[all …]
/linux/tools/power/x86/intel-speed-select/
H A Disst-display.c84 static void format_and_print_txt(FILE *outf, int level, char *header, in format_and_print_txt() argument
91 if (!level) in format_and_print_txt()
94 if (level == 1) { in format_and_print_txt()
97 for (i = 0; i < level - 1; ++i) in format_and_print_txt()
112 static void format_and_print(FILE *outf, int level, char *header, char *value) in format_and_print() argument
119 format_and_print_txt(outf, level, header, value); in format_and_print()
123 if (level == 0) { in format_and_print()
132 for (i = 0; i < level; ++i) in format_and_print()
136 if (last_level == level) in format_and_print()
140 if (last_level != level) in format_and_print()
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A Dl2_cache.json4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …refills into the level 2 cache. level 2 cache is a unified cache for data and instruction accesses…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …"PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated in…
40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.…
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
48 …"PublicDescription": "Counts cache line refills into the level 2 unified cache from any memory rea…
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dl2_cache.json4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …refills into the level 2 cache. level 2 cache is a unified cache for data and instruction accesses…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …"PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated in…
40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.…
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
H A Dmetrics.json89 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
96 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
103 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
117 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
124 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
131 …level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
138 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
145 …ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives a…
152 …"BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per …
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A Dextended.json7 …n": "A directory write to the Level-1 Instruction Cache directory where the returned cache line wa…
14 …tion": "A directory write to the Level-1 Data Cache directory where the installed cache line was s…
21 …n": "A directory write to the Level-1 Instruction Cache directory where the installed cache line w…
28 …ption": "A directory write to the Level-1 Data Cache directory where the installed cache line was …
35 …on": "A directory write to the Level-1 Instruction Cache directory where the installed cache line …
42 …ption": "A directory write to the Level-1 Data Cache directory where the installed cache line was …
49 …"PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed ca…
56 …"PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache…
63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in…
70 …scription": "A cache line in the Level-1 Instruction Cache has been invalidated by a store on the …
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-qcom-level.yaml4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
17 const: operating-points-v2-qcom-level
25 opp-level: true
27 qcom,opp-fuse-level:
29 A positive value representing the fuse corner/level associated with
31 corner/level. A fuse corner/level contains e.g. ref uV, min uV,
38 - opp-level
39 - qcom,opp-fuse-level
49 compatible = "operating-points-v2-qcom-level";
52 opp-level = <1>;
[all …]
/linux/arch/s390/kernel/
H A Dcache.c77 seq_printf(m, "level=%d ", cache->level); in show_cacheinfo()
88 static inline enum cache_type get_cache_type(struct cache_info *ci, int level) in get_cache_type() argument
90 if (level >= CACHE_MAX_LEVEL) in get_cache_type()
92 ci += level; in get_cache_type()
104 enum cache_type type, unsigned int level, int cpu) in ci_leaf_init() argument
112 this_leaf->level = level + 1; in ci_leaf_init()
114 this_leaf->coherency_line_size = ecag(EXTRACT_LINE_SIZE, level, ti); in ci_leaf_init()
115 this_leaf->ways_of_associativity = ecag(EXTRACT_ASSOCIATIVITY, level, ti); in ci_leaf_init()
116 this_leaf->size = ecag(EXTRACT_SIZE, level, ti); in ci_leaf_init()
128 unsigned int level = 0, leaves = 0; in init_cache_level() local
[all …]

12345678910>>...149