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/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A D	irqsrcs_dcn_1_0.h	30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 57 …DC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse [all …]
/linux/fs/nilfs2/
H A D	btree.c	26 int level = NILFS_BTREE_LEVEL_DATA; in nilfs_btree_alloc_path() local 32 for (; level < NILFS_BTREE_LEVEL_MAX; level++) { in nilfs_btree_alloc_path() 33 path[level].bp_bh = NULL; in nilfs_btree_alloc_path() 34 path[level].bp_sib_bh = NULL; in nilfs_btree_alloc_path() 35 path[level].bp_index = 0; in nilfs_btree_alloc_path() 36 path[level].bp_oldreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path() 37 path[level].bp_newreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path() 38 path[level].bp_op = NULL; in nilfs_btree_alloc_path() 47 int level in nilfs_btree_free_path() local 96 nilfs_btree_node_set_level(struct nilfs_btree_node * node,int level) nilfs_btree_node_set_level() argument 163 nilfs_btree_node_init(struct nilfs_btree_node * node,int flags,int level,int nchildren,int ncmax,const __u64 * keys,const __u64 * ptrs) nilfs_btree_node_init() argument 343 int level, flags, nchildren; nilfs_btree_node_broken() local 374 int level, flags, nchildren; nilfs_btree_root_broken() local 417 nilfs_btree_get_nonroot_node(const struct nilfs_btree_path * path,int level) nilfs_btree_get_nonroot_node() argument 423 nilfs_btree_get_sib_node(const struct nilfs_btree_path * path,int level) nilfs_btree_get_sib_node() argument 436 nilfs_btree_get_node(const struct nilfs_bmap * btree,const struct nilfs_btree_path * path,int level,int * ncmaxp) nilfs_btree_get_node() argument 451 nilfs_btree_bad_node(const struct nilfs_bmap * btree,struct nilfs_btree_node * node,int level) nilfs_btree_bad_node() argument 555 int level, index, found, ncmax, ret; nilfs_btree_do_lookup() local 615 int index, level, ncmax, ret; nilfs_btree_do_lookup_last() local 664 int index, next_adj, level; nilfs_btree_get_next_key() local 687 nilfs_btree_lookup(const struct nilfs_bmap * btree,__u64 key,int level,__u64 * ptrp) nilfs_btree_lookup() argument 712 int level = NILFS_BTREE_LEVEL_NODE_MIN; nilfs_btree_lookup_contig() local 794 nilfs_btree_promote_key(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 key) nilfs_btree_promote_key() argument 816 nilfs_btree_do_insert(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_do_insert() argument 843 nilfs_btree_carry_left(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_carry_left() argument 889 nilfs_btree_carry_right(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_carry_right() argument 936 nilfs_btree_split(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_split() argument 986 nilfs_btree_grow(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_grow() argument 1017 int level, ncmax; nilfs_btree_find_near() local 1070 int pindex, level, ncmax, ncblk, ret; nilfs_btree_prepare_insert() local 1216 int level; nilfs_btree_commit_insert() local 1239 int level, ret; nilfs_btree_insert() local 1266 nilfs_btree_do_delete(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_do_delete() argument 1291 nilfs_btree_borrow_left(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_borrow_left() argument 1323 nilfs_btree_borrow_right(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_borrow_right() argument 1356 nilfs_btree_concat_left(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_concat_left() argument 1382 nilfs_btree_concat_right(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_concat_right() argument 1407 nilfs_btree_shrink(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_shrink() argument 1431 nilfs_btree_nop(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,__u64 * keyp,__u64 * ptrp) nilfs_btree_nop() argument 1444 int pindex, dindex, level, ncmin, ncmax, ncblk, ret; nilfs_btree_prepare_delete() local 1574 int level; nilfs_btree_commit_delete() local 1591 int level, ret; nilfs_btree_delete() local 1915 nilfs_btree_propagate_p(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,struct buffer_head * bh) nilfs_btree_propagate_p() argument 1927 nilfs_btree_prepare_update_v(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,struct inode * dat) nilfs_btree_prepare_update_v() argument 1962 nilfs_btree_commit_update_v(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,struct inode * dat) nilfs_btree_commit_update_v() argument 1986 nilfs_btree_abort_update_v(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,struct inode * dat) nilfs_btree_abort_update_v() argument 2001 int level, ret; nilfs_btree_prepare_propagate_v() local 2037 int level; nilfs_btree_commit_propagate_v() local 2048 nilfs_btree_propagate_v(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,struct buffer_head * bh) nilfs_btree_propagate_v() argument 2087 int level, ret; nilfs_btree_propagate() local 2138 int level; nilfs_btree_add_dirty_buffer() local 2174 int level, i; nilfs_btree_lookup_dirty_buffers() local 2205 nilfs_btree_assign_p(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,struct buffer_head ** bh,sector_t blocknr,union nilfs_binfo * binfo) nilfs_btree_assign_p() argument 2247 nilfs_btree_assign_v(struct nilfs_bmap * btree,struct nilfs_btree_path * path,int level,struct buffer_head ** bh,sector_t blocknr,union nilfs_binfo * binfo) nilfs_btree_assign_v() argument 2284 int level, ret; nilfs_btree_assign() local 2342 nilfs_btree_mark(struct nilfs_bmap * btree,__u64 key,int level) nilfs_btree_mark() argument [all...]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This… 21 …rogress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in pr… 28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me… 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB… 49 …ress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss i… 56 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." 63 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." 70 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." 91 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is… [all …]
/linux/lib/zstd/compress/
H A D	clevels.h	27 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 / 28 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, / level 2 / 29 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, / level 3 / 30 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, / level 4 / 31 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, / level 5 / 32 { 21, 18, 19, 3, 5, 4, ZSTD_lazy }, / level 6 / 33 { 21, 19, 20, 4, 5, 8, ZSTD_lazy }, / level 7 / 34 { 21, 19, 20, 4, 5, 16, ZSTD_lazy2 }, / level 8 / 35 { 22, 20, 21, 4, 5, 16, ZSTD_lazy2 }, / level 9 / 36 { 22, 21, 22, 5, 5, 16, ZSTD_lazy2 }, / level 10 */ [all …]
/linux/fs/xfs/scrub/
H A D	btree.c	29 int level, in __xchk_btree_process_error() argument 51 trace_xchk_ifork_btree_op_error(sc, cur, level, in __xchk_btree_process_error() 54 trace_xchk_btree_op_error(sc, cur, level, in __xchk_btree_process_error() 65 int level, in xchk_btree_process_error() argument 68 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_process_error() 76 int level, in xchk_btree_xref_process_error() argument 79 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_xref_process_error() 88 int level, in __xchk_btree_set_corrupt() argument 95 trace_xchk_ifork_btree_error(sc, cur, level, in __xchk_btree_set_corrupt() 98 trace_xchk_btree_error(sc, cur, level, in __xchk_btree_set_corrupt() [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 28 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 35 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s… 49 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation … 56 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa… 70 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr… [all …]
/linux/arch/sparc/kernel/
H A D	cpumap.c	26 /* Increment rover every time level is visited / 34 int level; member 43 int start_index; / Index of first node of a level in a cpuinfo tree / 44 int end_index; / Index of last node of a level in a cpuinfo tree / 45 int num_nodes; / Number of nodes in a level in a cpuinfo tree / 51 / Offsets into nodes[] for each level of the tree / 52 struct cpuinfo_level level[CPUINFO_LVL_MAX]; member 96 static int cpuinfo_id(int cpu, int level) in cpuinfo_id() argument 100 switch (level) { in cpuinfo_id() 121 end index, and number of nodes for each level in the cpuinfo tree. The [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A D	cache.json	111 …"PublicDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from… 114 …"BriefDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from … 117 …"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a … 120 …"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a p… 123 …"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from t… 126 …"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from th… 141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t… 144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th… 147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t… 150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th… [all …]
/linux/arch/sparc/include/uapi/asm/
H A D	traps.h	`46 #define SP_TRAP_IRQ1 0x11 /* IRQ level 1 / 47 #define SP_TRAP_IRQ2 0x12 / IRQ level 2 / 48 #define SP_TRAP_IRQ3 0x13 / IRQ level 3 / 49 #define SP_TRAP_IRQ4 0x14 / IRQ level 4 / 50 #define SP_TRAP_IRQ5 0x15 / IRQ level 5 / 51 #define SP_TRAP_IRQ6 0x16 / IRQ level 6 / 52 #define SP_TRAP_IRQ7 0x17 / IRQ level 7 / 53 #define SP_TRAP_IRQ8 0x18 / IRQ level 8 / 54 #define SP_TRAP_IRQ9 0x19 / IRQ level 9 / 55 #define SP_TRAP_IRQ10 0x1a / IRQ level 10 */ [all …]`
/linux/fs/bcachefs/
H A D	btree_locking.h	42 unsigned level) in btree_node_locked_type() argument 44 return BTREE_NODE_UNLOCKED + ((path->nodes_locked >> (level << 1)) & 3); in btree_node_locked_type() 62 static inline bool btree_node_locked(struct btree_path *path, unsigned level) in btree_node_locked() argument 64 return btree_node_locked_type(path, level) != BTREE_NODE_UNLOCKED; in btree_node_locked() 68 unsigned level, in mark_btree_node_locked_noreset() argument 75 path->nodes_locked &= ~(3U << (level << 1)); in mark_btree_node_locked_noreset() 76 path->nodes_locked \|= (type + 1) << (level << 1); in mark_btree_node_locked_noreset() 81 unsigned level, in mark_btree_node_locked() argument 84 mark_btree_node_locked_noreset(path, level, (enum btree_node_locked_type) type); in mark_btree_node_locked() 86 path->l[level].lock_taken_time = local_clock(); in mark_btree_node_locked() [all …]
/linux/arch/arm64/kernel/
H A D	cacheinfo.c	13 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ 24 static inline enum cache_type get_cache_type(int level) in get_cache_type() argument 28 if (level > MAX_CACHE_LEVEL) in get_cache_type() 31 return CLIDR_CTYPE(clidr, level); in get_cache_type() 35 enum cache_type type, unsigned int level) in ci_leaf_init() argument 37 this_leaf->level = level; in ci_leaf_init() 43 unsigned int ctype, level, leaves; in detect_cache_level() local 45 for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { in detect_cache_level() 46 ctype = get_cache_type(level); in detect_cache_level() 48 level--; in detect_cache_level() [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 21 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s… 28 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa… 35 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s… 42 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 49 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w… 56 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache… 63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in… 70 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th… 28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me… 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB… 42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s… 56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach… 63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa… 70 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." 77 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." 84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	cache.json	105 …"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from t… 108 …"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from th… 111 …"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a … 114 …"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a p… 117 …"PublicDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills f… 120 …"BriefDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills fr… 123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t… 126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th… 129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each … 132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e… [all …]
/linux/arch/arm64/boot/dts/rockchip/
H A D	rockchip-pinconf.dtsi	23 pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { 29 pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { 35 pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { 41 pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { 47 pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { 53 pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { 59 pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { 65 pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { 71 pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { 77 pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A D	extended.json	7 …ption": "A directory write to the Level-1 Data Cache directory where the returned cache line was s… 14 …n": "A directory write to the Level-1 Instruction Cache directory where the returned cache line wa… 21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache." 42 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc… 49 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc… 56 … "A directory write to the Level-1 Instruction Cache directory where the returned cache line was s… 63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in… 70 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc… [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th… 28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me… 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB… 42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s… 56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach… 63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa… 70 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." 77 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." 84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." [all …]
/linux/arch/riscv/kernel/
H A D	cacheinfo.c	27 static struct cacheinfo get_cacheinfo(u32 level, enum cache_type type) in get_cacheinfo() argument 44 if (this_leaf->level == level && this_leaf->type == type) in get_cacheinfo() 51 uintptr_t get_cache_size(u32 level, enum cache_type type) in get_cache_size() argument 53 struct cacheinfo this_leaf = get_cacheinfo(level, type); in get_cache_size() 58 uintptr_t get_cache_geometry(u32 level, enum cache_type type) in get_cache_geometry() argument 60 struct cacheinfo *this_leaf = get_cacheinfo(level, type); in get_cache_geometry() 68 enum cache_type type, unsigned int level) in ci_leaf_init() argument 70 this_leaf->level = level; in ci_leaf_init() 84 int levels = 1, level = 1; in populate_cache_leaves() local 96 for (; level <= this_cpu_ci->num_levels; level++) { in populate_cache_leaves() [all …]
/linux/drivers/gpu/drm/xe/
H A D	xe_pt_walk.h	32 * different levels, starting out with the leaf level 0 37 /** @max_level: Highest populated level in @sizes / 54 @level: The level of @parent. 64 unsigned int level, u64 addr, u64 next, 75 * to descending to the next level. The returned value of the action 81 * after return from descending to the next level. The returned value 87 int xe_pt_walk_range(struct xe_ptw parent, unsigned int level, 90 int xe_pt_walk_shared(struct xe_ptw parent, unsigned int level, 94 * xe_pt_covers - Whether the address range covers an entire entry in @level 97 * @level: Page table level. [all …]
H A D	xe_lmtt.c	30 * See `Two-Level LMTT Structure`_ and `Multi-Level LMTT Structure`_. 56 static struct xe_lmtt_pt lmtt_pt_alloc(struct xe_lmtt lmtt, unsigned int level) in lmtt_pt_alloc() argument 58 unsigned int num_entries = level ? lmtt->ops->lmtt_pte_num(level) : 0; in lmtt_pt_alloc() 70 PAGE_ALIGN(lmtt->ops->lmtt_pte_size(level) * in lmtt_pt_alloc() 71 lmtt->ops->lmtt_pte_num(level)), in lmtt_pt_alloc() 82 pt->level = level; in lmtt_pt_alloc() 116 unsigned int num_entries = lmtt->ops->lmtt_pte_num(pd->level); in lmtt_fini_pd() 148 * variants are `Two-Level LMTT Structure`_ and `Multi-Level LMTT Structure`_. 222 unsigned int level = pt->level; in lmtt_write_pte() local 224 lmtt_assert(lmtt, idx <= lmtt->ops->lmtt_pte_num(level)); in lmtt_write_pte() [all …]
/linux/tools/power/x86/intel-speed-select/
H A D	isst-display.c	84 static void format_and_print_txt(FILE outf, int level, char header, in format_and_print_txt() argument 91 if (!level) in format_and_print_txt() 94 if (level == 1) { in format_and_print_txt() 97 for (i = 0; i < level - 1; ++i) in format_and_print_txt() 112 static void format_and_print(FILE outf, int level, char header, char *value) in format_and_print() argument 119 format_and_print_txt(outf, level, header, value); in format_and_print() 123 if (level == 0) { in format_and_print() 132 for (i = 0; i < level; ++i) in format_and_print() 136 if (last_level == level) in format_and_print() 140 if (last_level != level) in format_and_print() [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	cache.json	107 "PublicDescription": "Level 1 data or unified cache demand access", 110 "BriefDescription": "Level 1 data or unified cache demand access" 113 "PublicDescription": "Level 1 data or unified cache preload or prefetch", 116 "BriefDescription": "Level 1 data or unified cache preload or prefetch" 119 "PublicDescription": "Level 1 data or unified cache refill, preload or prefetch", 122 "BriefDescription": "Level 1 data or unified cache refill, preload or prefetch" 149 "PublicDescription": "Level 1 prefetcher, load prefetch requests generated", 152 "BriefDescription": "Level 1 prefetcher, load prefetch requests generated" 155 "PublicDescription": "Level 1 prefetcher, load prefetch fills into the level [all...]
/linux/drivers/scsi/
H A D	scsi_logging.h	47 #define SCSI_CHECK_LOGGING(SHIFT, BITS, LEVEL, CMD) \ argument 49 if (unlikely((SCSI_LOG_LEVEL(SHIFT, BITS)) > (LEVEL))) \ 56 #define SCSI_CHECK_LOGGING(SHIFT, BITS, LEVEL, CMD) do { } while (0) argument 64 #define SCSI_LOG_ERROR_RECOVERY(LEVEL,CMD) \ argument 65 SCSI_CHECK_LOGGING(SCSI_LOG_ERROR_SHIFT, SCSI_LOG_ERROR_BITS, LEVEL,CMD); 66 #define SCSI_LOG_TIMEOUT(LEVEL,CMD) \ argument 67 SCSI_CHECK_LOGGING(SCSI_LOG_TIMEOUT_SHIFT, SCSI_LOG_TIMEOUT_BITS, LEVEL,CMD); 68 #define SCSI_LOG_SCAN_BUS(LEVEL,CMD) \ argument 69 SCSI_CHECK_LOGGING(SCSI_LOG_SCAN_SHIFT, SCSI_LOG_SCAN_BITS, LEVEL,CMD); 70 #define SCSI_LOG_MLQUEUE(LEVEL,CMD) \ argument [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	l2_cache.json	4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access… 8 …refills into the level 2 cache. level 2 cache is a unified cache for data and instruction accesses… 20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an… 24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a… 28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access… 32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access… 36 …"PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated in… 40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.… 44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca… 48 …"PublicDescription": "Counts cache line refills into the level 2 unified cache from any memory rea…
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A D	l2_cache.json	4 "PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level data cache or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache." 8 "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses." 16 "PublicDescription": "Counts level 2 cache line allocates that do not fetch data from outside the level 2 data or unified cache." 20 "PublicDescription": "Counts level [all...]

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