xref: /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json (revision 36ec807b627b4c0a0a382f0ae48eac7187d14b2b)

[
    {
        "ArchStdEvent": "L1D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_INVAL",
        "Errata": "Errata AC04_CPU_1",
        "BriefDescription": "L1D cache invalidate. Impacted by errata -"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
    },
    {
        "ArchStdEvent": "L2D_CACHE_INVAL"
    },
    {
        "ArchStdEvent": "L1I_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L1I_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L1D_CACHE"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L1I_CACHE"
    },
    {
        "ArchStdEvent": "L2D_CACHE"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB"
    },
    {
        "ArchStdEvent": "L1D_TLB"
    },
    {
        "ArchStdEvent": "L1I_TLB"
    },
    {
        "ArchStdEvent": "L2D_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L2I_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L2D_TLB"
    },
    {
        "ArchStdEvent": "L2I_TLB"
    },
    {
        "ArchStdEvent": "DTLB_WALK"
    },
    {
        "ArchStdEvent": "ITLB_WALK"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
    },
    {
        "ArchStdEvent": "L1D_CACHE_LMISS_RD"
    },
    {
        "ArchStdEvent": "L1I_CACHE_LMISS"
    },
    {
        "ArchStdEvent": "L2D_CACHE_LMISS_RD"
    },
    {
        "PublicDescription": "Level 1 data or unified cache demand access",
        "EventCode": "0x8140",
        "EventName": "L1D_CACHE_RW",
        "BriefDescription": "Level 1 data or unified cache demand access"
    },
    {
        "PublicDescription": "Level 1 data or unified cache preload or prefetch",
        "EventCode": "0x8142",
        "EventName": "L1D_CACHE_PRFM",
        "BriefDescription": "Level 1 data or unified cache preload or prefetch"
    },
    {
        "PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
        "EventCode": "0x8146",
        "EventName": "L1D_CACHE_REFILL_PRFM",
        "BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
    },
    {
        "ArchStdEvent": "L1D_TLB_RD"
    },
    {
        "ArchStdEvent": "L1D_TLB_WR"
    },
    {
        "ArchStdEvent": "L2D_TLB_REFILL_RD"
    },
    {
        "ArchStdEvent": "L2D_TLB_REFILL_WR"
    },
    {
        "ArchStdEvent": "L2D_TLB_RD"
    },
    {
        "ArchStdEvent": "L2D_TLB_WR"
    },
    {
        "PublicDescription": "L1D TLB miss",
        "EventCode": "0xD600",
        "EventName": "L1D_TLB_MISS",
        "BriefDescription": "L1D TLB miss"
    },
    {
        "PublicDescription": "Level 1 prefetcher, load prefetch requests generated",
        "EventCode": "0xd606",
        "EventName": "L1_PREFETCH_LD_GEN",
        "BriefDescription": "Level 1 prefetcher, load prefetch requests generated"
    },
    {
        "PublicDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache",
        "EventCode": "0xd607",
        "EventName": "L1_PREFETCH_LD_FILL",
        "BriefDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache"
    },
    {
        "PublicDescription": "Level 1 prefetcher, load prefetch to level 2 generated",
        "EventCode": "0xd608",
        "EventName": "L1_PREFETCH_L2_REQ",
        "BriefDescription": "Level 1 prefetcher, load prefetch to level 2 generated"
    },
    {
        "PublicDescription": "L1 prefetcher, distance was reset",
        "EventCode": "0xd609",
        "EventName": "L1_PREFETCH_DIST_RST",
        "BriefDescription": "L1 prefetcher, distance was reset"
    },
    {
        "PublicDescription": "L1 prefetcher, distance was increased",
        "EventCode": "0xd60a",
        "EventName": "L1_PREFETCH_DIST_INC",
        "BriefDescription": "L1 prefetcher, distance was increased"
    },
    {
        "PublicDescription": "Level 1 prefetcher, table entry is trained",
        "EventCode": "0xd60b",
        "EventName": "L1_PREFETCH_ENTRY_TRAINED",
        "BriefDescription": "Level 1 prefetcher, table entry is trained"
    },
    {
        "PublicDescription": "L1 data cache refill - Read or Write",
        "EventCode": "0xd60e",
        "EventName": "L1D_CACHE_REFILL_RW",
        "BriefDescription": "L1 data cache refill - Read or Write"
    },
    {
        "PublicDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills",
        "EventCode": "0xD701",
        "EventName": "L2C_INST_REFILL",
        "BriefDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills"
    },
    {
        "PublicDescription": "Level 2 cache refill from data-side miss, including DMMU refills",
        "EventCode": "0xD702",
        "EventName": "L2C_DATA_REFILL",
        "BriefDescription": "Level 2 cache refill from data-side miss, including DMMU refills"
    },
    {
        "PublicDescription": "Level 2 cache prefetcher, load prefetch requests generated",
        "EventCode": "0xD703",
        "EventName": "L2_PREFETCH_REQ",
        "BriefDescription": "Level 2 cache prefetcher, load prefetch requests generated"
    }
]