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/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	datasource.json	5 "BriefDescription": "Load finished without experiencing an L1 miss." 10 …"BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and … 15 …"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local cor… 20 …"BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 du… 25 "BriefDescription": "Load missed L1, counted at finish time." 35 …"BriefDescription": "An instruction fetch hit in the L1. Each fetch group contains 8 instructions.… 65 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a … 75 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a … 80 …sor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss… 85 …"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local cor… [all …]
/linux/Documentation/networking/
H A D	tls-offload-layers.svg	`1 …l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.82812…`
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A D	memory.json	40 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.", 46 …"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 1… 52 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.", 58 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.", 64 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pa… 70 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coale… 76 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pa… 82 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pa… 88 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all p… 94 "BriefDescription": "L1 DTLB misses for all page sizes.", [all …]
H A D	recommended.json	23 "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).", 29 "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).", 47 "BriefDescription": "L2 cache misses from L1 instruction cache misses.", 53 "BriefDescription": "L2 cache misses from L1 data cache misses.", 71 "BriefDescription": "L2 cache hits from L1 instruction cache misses.", 77 "BriefDescription": "L2 cache hits from L1 data cache misses.", 120 "BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node.", 126 "BriefDescription": "L1 data cache fills from a different NUMA node.", 132 "BriefDescription": "L1 data cache fills from within the same CCX.", 138 "BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node.", [all …]
/linux/arch/sparc/kernel/
H A D	rtrap_64.S	`62 andn %l1, %o0, %l1 85 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 87 and %l1, %l4, %l4 88 andn %l1, %l4, %l1 96 rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 98 and %l1, %l4, %l4 99 andn %l1, %l4, %l1 115 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 118 and %l1, %l4, %l4 119 andn %l1, %l4, %l1 [all …]`
/linux/tools/perf/pmu-events/
H A D	empty-pmu-events.c	23 /* offset=13 / "l1-dcache\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000" 24 / offset=99 / "l1-dcache-load\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000" 25 / offset=190 / "l1-dcache-load-refs\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000" 26 / offset=286 / "l1-dcache-load-reference\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000" 27 / offset=387 / "l1-dcache-load-ops\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000" 28 / offset=482 / "l1-dcache-load-access\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000" 29 / offset=580 / "l1-dcache-load-misses\000legacy cache\000Level 1 data cache read misses\000legacy-cache-config=0x10000\000\00000\000\000\000\000\000" 30 / offset=682 / "l1-dcache-load-miss\000legacy cache\000Level 1 data cache read misses\000legacy-cache-config=0x10000\000\00010\000\000\000\000\000" 31 / offset=782 / "l1-dcache-loads\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00000\000\000\000\000\000" 32 / offset=874 */ "l1 [all...]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
H A D	cache.json	7 …"PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This… 11 …ess which causes data to be read from outside the L1, including accesses which do not allocate int… 15 …ny load or store operation or page table walk access which looks up in the L1 data cache. In parti… 19 …"PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includ… 23 …p cache access. This event counts any instruction fetch which accesses the L1 instruction cache or… 27 …"PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3.… 31 …n": "This event counts any transaction from L1 which looks up in the L2 cache, and any write-back … 35 …": "L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to… 39 …ch do not write data outside of the core and snoops which return data from the L1 are not counted", 43 …t cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate… [all …]
/linux/Documentation/virt/kvm/x86/
H A D	running-nested-guests.rst	19 \| L1 (Guest Hypervisor) \| 33 - L1 – level-1 guest; a VM running on L0; also called the "guest 36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest" 45 metal, running the LPAR hypervisor), L1 (host hypervisor), L2 49 L1, and L2) for all architectures; and will largely focus on 148 able to start an L1 guest with:: 175 2. The guest hypervisor (L1) must be provided with the ``sie`` CPU 179 3. Now the KVM module can be loaded in the L1 (guest hypervisor):: 187 Migrating an L1 guest, with a live nested guest in it, to another 191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	memory.json	21 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 30 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 177 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 183 …"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that w… 188 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 194 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 199 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 205 …"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that w… 210 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 216 …"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that w… [all …]
H A D	cache.json	74 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 358 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 367 "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 452 "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", 456 "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)", 551 "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", 556 "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. Available PDIST counters: 0", 561 "BriefDescription": "Retired load instructions with L1 cach [all...]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	memory.json	21 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 30 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 177 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 183 …"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that w… 188 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 194 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 199 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 205 …"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that w… 210 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 216 …"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that w… [all …]
H A D	cache.json	74 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 358 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 367 "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 452 "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", 456 "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)", 560 "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", 565 "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. Available PDIST counters: 0", 570 "BriefDescription": "Retired load instructions with L1 cach [all...]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	recommended.json	12 "BriefDescription": "All L1 Data Cache Accesses", 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", 78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", 124 "BriefDescription": "L1 Data Cache Fills: From Memory", 130 "BriefDescription": "L1 Data Cache Fills: From Remote Node", 136 "BriefDescription": "L1 Data Cache Fills: From within same CCX", [all …]
H A D	branch.json	`5 "BriefDescription": "L1 Branch Prediction Overrides Existing Prediction (speculative)." 27 "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.", 33 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB… 39 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB… 45 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB…`
/linux/tools/perf/pmu-events/arch/x86/amdzen6/
H A D	recommended.json	25 …"BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch) per t… 32 …"BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch) per thousand… 53 … "BriefDescription": "L2 cache misses from L1 instruction cache misses per thousand instructions.", 60 "BriefDescription": "L2 cache misses from L1 data cache misses per thousand instructions.", 81 "BriefDescription": "L2 cache hits from L1 instruction cache misses per thousand instructions.", 88 "BriefDescription": "L2 cache hits from L1 data cache misses per thousand instructions.", 141 …"BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node per thousand instructi… 148 "BriefDescription": "L1 data cache fills from a different NUMA node per thousand instructions.", 155 "BriefDescription": "L1 data cache fills from within the same CCX per thousand instructions.", 162 …"BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node per thousand inst… [all …]
H A D	branch-prediction.json	5 "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB." 10 …"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks r… 16 …"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks r… 22 …"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks r… 28 …"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks r… 34 …"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks r… 55 …"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages (16k pa… 61 "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.", 67 "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.", 73 "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
/linux/Documentation/devicetree/bindings/regulator/
H A D	qcom,smd-rpm-regulator.yaml	27 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, 30 For pm6125 s1, s2, s3, s4, s5, s6, s7, s8, l1, l2, l3, l5, l6, l7, l8, l9, 33 For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22, 36 For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob 38 For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, 44 For pm8909, s1, s2, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, 47 For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, 50 For pm8937, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, 53 For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, 57 For pm8950 and pm8953, s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6, [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	memory.json	117 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 127 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 137 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 147 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 157 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 177 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 187 …n": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches an… 237 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 247 …clusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches an… 277 …"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFET… [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	memory.json	30 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 39 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 198 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 204 …"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that w… 209 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 215 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 220 …"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that we… 226 …"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that w… 242 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 248 …n": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches. A… [all …]
/linux/tools/testing/selftests/powerpc/pmu/event_code_tests/
H A D	group_constraint_cache_test.c	13 /* All L1 D cache load references counted at finish, gated by reject / 15 / Load Missed L1 / 17 / Load Missed L1 / 23 Monitor Mode Control Register 1 (MMCR1: 16-17) for l1 cache. 34 /* Init the events for the group contraint check for l1 cache select bits / in group_constraint_cache() 40 / Expected to fail as sibling event doesn't request same l1 cache select bits as leader / in group_constraint_cache() 45 / Init the event for the group contraint l1 cache select test / in group_constraint_cache() 48 / Expected to succeed as sibling event request same l1 cache select bits as leader */ in group_constraint_cache()
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A D	core-imp-def.json	267 "PublicDescription": "Dispatch stall due to L1 instruction cache miss", 270 "BriefDescription": "Dispatch stall due to L1 instruction cache miss" 273 "PublicDescription": "Dispatch stall due to L1 instruction TLB miss", 276 "BriefDescription": "Dispatch stall due to L1 instruction TLB miss" 279 "PublicDescription": "Dispatch stall due to L1 data cache miss", 282 "BriefDescription": "Dispatch stall due to L1 data cache miss" 285 "PublicDescription": "Dispatch stall due to L1 data TLB miss", 288 "BriefDescription": "Dispatch stall due to L1 data TLB miss" 459 "PublicDescription": "L1 prefetcher, load prefetch requests generated", 462 "BriefDescription": "L1 prefetcher, load prefetch requests generated" [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	recommended.json	12 "BriefDescription": "All L1 Data Cache Accesses", 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", 78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", 110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio", 117 "BriefDescription": "L1 ITLB Misses", 130 "BriefDescription": "L1 DTLB Misses",
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	recommended.json	12 "BriefDescription": "All L1 Data Cache Accesses", 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", 78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", 110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio", 117 "BriefDescription": "L1 ITLB Misses", 130 "BriefDescription": "L1 DTLB Misses",
/linux/drivers/media/pci/intel/ipu6/
H A D	ipu6.h	146 * used to fill the L1 and L2 caches with the trash buffer translations. ZLW 148 * advance to the L1 and L2 caches without triggering any memory operations. 150 * In MMU V2, L1 -> 16 streams and 64 blocks, maximum 16 blocks per stream 151 * One L1 block has 16 entries, hence points to 16 * 4K pages 153 * One L2 block maps to 1024 L1 entries, hence points to 4MB address range 163 /* One L2 entry maps 1024 L1 entries and one L1 entry per page / 167 / Max L1 blocks per stream / 170 / Entries per L1 block / 176 In some of the IPU6 MMUs, there is provision to configure L1 and L2 page 177 * table caches. Both these L1 and L2 caches are divided into multiple sections [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	cache.json	3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th… 7 …"PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by t… 67 …s include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If th… 76 …s include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If th… 180 "BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.", 186 …"PublicDescription": "Counts the number of load uops retired that hit in the L1 data cache. Availa… 191 … "BriefDescription": "Counts the number of load uops retired that miss in the L1 data cache.", 197 …"PublicDescription": "Counts the number of load uops retired that miss in the L1 data cache. Avail… 378 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of r… 384 …"PublicDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of … [all …]

12 3 4 5 6 7 8 9 10 >>...37