xref: /linux/tools/perf/pmu-events/arch/x86/amdzen6/branch-prediction.json (revision c7decec2f2d2ab0366567f9e30c0e1418cece43f) 
1[
2  {
3    "EventName": "bp_l1_tlb_miss_l2_tlb_hit",
4    "EventCode": "0x84",
5    "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
6  },
7  {
8    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
9    "EventCode": "0x85",
10    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 4k pages.",
11    "UMask": "0x01"
12  },
13  {
14    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
15    "EventCode": "0x85",
16    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 2M pages.",
17    "UMask": "0x02"
18  },
19  {
20    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
21    "EventCode": "0x85",
22    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for 1G pages.",
23    "UMask": "0x04"
24  },
25  {
26    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
27    "EventCode": "0x85",
28    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for coalesced pages (16k pages created from four adjacent 4k pages).",
29    "UMask": "0x08"
30  },
31  {
32    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
33    "EventCode": "0x85",
34    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks requested) for all page sizes.",
35    "UMask": "0x0f"
36  },
37  {
38    "EventName": "bp_pipe_correct",
39    "EventCode": "0x8b",
40    "BriefDescription": "Branch predictor pipeline flushes due to internal conditions such as a second level prediction structure."
41  },
42  {
43    "EventName": "bp_var_target_pred",
44    "EventCode": "0x8e",
45    "BriefDescription": "Indirect predictions (branch used the indirect predictor to make a prediction)."
46  },
47  {
48    "EventName": "bp_early_redir",
49    "EventCode": "0x91",
50    "BriefDescription": "Early redirects sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected."
51  },
52  {
53    "EventName": "bp_l1_tlb_fetch_hit.if4k",
54    "EventCode": "0x94",
55    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages (16k pages created from four adjacent 4k pages).",
56    "UMask": "0x01"
57  },
58  {
59    "EventName": "bp_l1_tlb_fetch_hit.if2m",
60    "EventCode": "0x94",
61    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
62    "UMask": "0x02"
63  },
64  {
65    "EventName": "bp_l1_tlb_fetch_hit.if1g",
66    "EventCode": "0x94",
67    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
68    "UMask": "0x04"
69  },
70  {
71    "EventName": "bp_l1_tlb_fetch_hit.all",
72    "EventCode": "0x94",
73    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
74    "UMask": "0x07"
75  },
76  {
77    "EventName": "bp_fe_redir.resync",
78    "EventCode": "0x9f",
79    "BriefDescription": "Redirects of the pipeline frontend caused by resyncs. These are retire time pipeline restarts.",
80    "UMask": "0x01"
81  },
82  {
83    "EventName": "bp_fe_redir.ex_redir",
84    "EventCode": "0x9f",
85    "BriefDescription": "Redirects of the pipeline frontend caused by mispredicts. These are used for branch direction correction and handling indirect branch target mispredicts.",
86    "UMask": "0x02"
87  },
88  {
89    "EventName": "bp_fe_redir.all",
90    "EventCode": "0x9f",
91    "BriefDescription": "Redirects of the pipeline frontend caused by any reason."
92  }
93]
94