xref: /linux/tools/perf/pmu-events/arch/x86/amdzen6/recommended.json (revision c7decec2f2d2ab0366567f9e30c0e1418cece43f) 
1[
2  {
3    "MetricName": "branch_misprediction_rate",
4    "BriefDescription": "Execution-time branch misprediction rate (non-speculative).",
5    "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
6    "MetricGroup": "branch_prediction",
7    "ScaleUnit": "1per_branch"
8  },
9  {
10    "MetricName": "all_data_cache_accesses_pti",
11    "BriefDescription": "All data cache accesses per thousand instructions.",
12    "MetricExpr": "ls_dispatch.all / instructions",
13    "MetricGroup": "l1_dcache",
14    "ScaleUnit": "1e3per_1k_instr"
15  },
16  {
17    "MetricName": "all_l2_cache_accesses_pti",
18    "BriefDescription": "All L2 cache accesses per thousand instructions.",
19    "MetricExpr": "(l2_request_g1.no_pf_all + l2_pf_hit_l2.l2_hwpf + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions",
20    "MetricGroup": "l2_cache",
21    "ScaleUnit": "1e3per_1k_instr"
22  },
23  {
24    "MetricName": "l2_cache_accesses_from_l1_ic_misses_pti",
25    "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch) per thousand instructions.",
26    "MetricExpr": "l2_request_g1.cacheable_ic_read / instructions",
27    "MetricGroup": "l2_cache",
28    "ScaleUnit": "1e3per_1k_instr"
29  },
30  {
31    "MetricName": "l2_cache_accesses_from_l1_dc_misses_pti",
32    "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch) per thousand instructions.",
33    "MetricExpr": "l2_request_g1.dc_all / instructions",
34    "MetricGroup": "l2_cache",
35    "ScaleUnit": "1e3per_1k_instr"
36  },
37  {
38    "MetricName": "l2_cache_accesses_from_l2_hwpf_pti",
39    "BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher per thousand instructions.",
40    "MetricExpr": "(l2_pf_hit_l2.l1_dc_l2_hwpf + l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions",
41    "MetricGroup": "l2_cache",
42    "ScaleUnit": "1e3per_1k_instr"
43  },
44  {
45    "MetricName": "all_l2_cache_misses_pti",
46    "BriefDescription": "All L2 cache misses per thousand instructions.",
47    "MetricExpr": "(l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions",
48    "MetricGroup": "l2_cache",
49    "ScaleUnit": "1e3per_1k_instr"
50  },
51  {
52    "MetricName": "l2_cache_misses_from_l1_ic_miss_pti",
53    "BriefDescription": "L2 cache misses from L1 instruction cache misses per thousand instructions.",
54    "MetricExpr": "l2_cache_req_stat.ic_fill_miss / instructions",
55    "MetricGroup": "l2_cache",
56    "ScaleUnit": "1e3per_1k_instr"
57  },
58  {
59    "MetricName": "l2_cache_misses_from_l1_dc_miss_pti",
60    "BriefDescription": "L2 cache misses from L1 data cache misses per thousand instructions.",
61    "MetricExpr": "l2_cache_req_stat.ls_rd_blk_c / instructions",
62    "MetricGroup": "l2_cache",
63    "ScaleUnit": "1e3per_1k_instr"
64  },
65  {
66    "MetricName": "l2_cache_misses_from_l2_hwpf_pti",
67    "BriefDescription": "L2 cache misses from L2 cache hardware prefetcher per thousand instructions.",
68    "MetricExpr": "(l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions",
69    "MetricGroup": "l2_cache",
70    "ScaleUnit": "1e3per_1k_instr"
71  },
72  {
73    "MetricName": "all_l2_cache_hits_pti",
74    "BriefDescription": "All L2 cache hits per thousand instructions.",
75    "MetricExpr": "(l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.l2_hwpf) / instructions",
76    "MetricGroup": "l2_cache",
77    "ScaleUnit": "1e3per_1k_instr"
78  },
79  {
80    "MetricName": "l2_cache_hits_from_l1_ic_miss_pti",
81    "BriefDescription": "L2 cache hits from L1 instruction cache misses per thousand instructions.",
82    "MetricExpr": "l2_cache_req_stat.ic_hit_in_l2 / instructions",
83    "MetricGroup": "l2_cache",
84    "ScaleUnit": "1e3per_1k_instr"
85  },
86  {
87    "MetricName": "l2_cache_hits_from_l1_dc_miss_pti",
88    "BriefDescription": "L2 cache hits from L1 data cache misses per thousand instructions.",
89    "MetricExpr": "l2_cache_req_stat.dc_hit_in_l2 / instructions",
90    "MetricGroup": "l2_cache",
91    "ScaleUnit": "1e3per_1k_instr"
92  },
93  {
94    "MetricName": "l2_cache_hits_from_l2_hwpf_pti",
95    "BriefDescription": "L2 cache hits from L2 cache hardware prefetcher per thousand instructions.",
96    "MetricExpr": "l2_pf_hit_l2.l1_dc_l2_hwpf / instructions",
97    "MetricGroup": "l2_cache",
98    "ScaleUnit": "1e3per_1k_instr"
99  },
100  {
101    "MetricName": "l3_cache_accesses",
102    "BriefDescription": "L3 cache accesses.",
103    "MetricExpr": "l3_lookup_state.all_coherent_accesses_to_l3",
104    "MetricGroup": "l3_cache"
105  },
106  {
107    "MetricName": "l3_misses",
108    "BriefDescription": "L3 misses (including cacheline state change requests).",
109    "MetricExpr": "l3_lookup_state.l3_miss",
110    "MetricGroup": "l3_cache"
111  },
112  {
113    "MetricName": "l3_read_miss_latency",
114    "BriefDescription": "Average L3 read miss latency (in core clocks).",
115    "MetricExpr": "(l3_xi_sampled_latency.all * 10) / l3_xi_sampled_latency_requests.all",
116    "MetricGroup": "l3_cache",
117    "ScaleUnit": "1ns"
118  },
119  {
120    "MetricName": "l3_read_miss_latency_for_local_dram",
121    "BriefDescription": "Average L3 read miss latency (in core clocks) for local DRAM.",
122    "MetricExpr": "(l3_xi_sampled_latency.dram_near * 10) / l3_xi_sampled_latency_requests.dram_near",
123    "MetricGroup": "l3_cache",
124    "ScaleUnit": "1ns"
125  },
126  {
127    "MetricName": "l3_read_miss_latency_for_remote_dram",
128    "BriefDescription": "Average L3 read miss latency (in core clocks) for remote DRAM.",
129    "MetricExpr": "(l3_xi_sampled_latency.dram_far * 10) / l3_xi_sampled_latency_requests.dram_far",
130    "MetricGroup": "l3_cache",
131    "ScaleUnit": "1ns"
132  },
133  {
134    "MetricName": "op_cache_fetch_miss_ratio",
135    "BriefDescription": "Op cache miss ratio for all fetches.",
136    "MetricExpr": "d_ratio(op_cache_hit_miss.miss, op_cache_hit_miss.all)",
137    "ScaleUnit": "100%"
138  },
139  {
140    "MetricName": "l1_data_cache_fills_from_memory_pti",
141    "BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node per thousand instructions.",
142    "MetricExpr": "ls_any_fills_from_sys.dram_io_all / instructions",
143    "MetricGroup": "l1_dcache",
144    "ScaleUnit": "1e3per_1k_instr"
145  },
146  {
147    "MetricName": "l1_data_cache_fills_from_remote_node_pti",
148    "BriefDescription": "L1 data cache fills from a different NUMA node per thousand instructions.",
149    "MetricExpr": "ls_any_fills_from_sys.far_all / instructions",
150    "MetricGroup": "l1_dcache",
151    "ScaleUnit": "1e3per_1k_instr"
152  },
153  {
154    "MetricName": "l1_data_cache_fills_from_same_ccx_pti",
155    "BriefDescription": "L1 data cache fills from within the same CCX per thousand instructions.",
156    "MetricExpr": "ls_any_fills_from_sys.local_all / instructions",
157    "MetricGroup": "l1_dcache",
158    "ScaleUnit": "1e3per_1k_instr"
159  },
160  {
161    "MetricName": "l1_data_cache_fills_from_different_ccx_pti",
162    "BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node per thousand instructions.",
163    "MetricExpr": "ls_any_fills_from_sys.remote_cache / instructions",
164    "MetricGroup": "l1_dcache",
165    "ScaleUnit": "1e3per_1k_instr"
166  },
167  {
168    "MetricName": "all_l1_data_cache_fills_pti",
169    "BriefDescription": "All L1 data cache fills per thousand instructions.",
170    "MetricExpr": "ls_any_fills_from_sys.all / instructions",
171    "MetricGroup": "l1_dcache",
172    "ScaleUnit": "1e3per_1k_instr"
173  },
174  {
175    "MetricName": "l1_demand_data_cache_fills_from_local_l2_pti",
176    "BriefDescription": "L1 demand data cache fills from local L2 cache per thousand instructions.",
177    "MetricExpr": "ls_dmnd_fills_from_sys.local_l2 / instructions",
178    "MetricGroup": "l1_dcache",
179    "ScaleUnit": "1e3per_1k_instr"
180  },
181  {
182    "MetricName": "l1_demand_data_cache_fills_from_same_ccx_pti",
183    "BriefDescription": "L1 demand data cache fills from within the same CCX per thousand instructions.",
184    "MetricExpr": "ls_dmnd_fills_from_sys.local_ccx / instructions",
185    "MetricGroup": "l1_dcache",
186    "ScaleUnit": "1e3per_1k_instr"
187  },
188  {
189    "MetricName": "l1_demand_data_cache_fills_from_near_cache_pti",
190    "BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node per thousand instructions.",
191    "MetricExpr": "ls_dmnd_fills_from_sys.near_cache / instructions",
192    "MetricGroup": "l1_dcache",
193    "ScaleUnit": "1e3per_1k_instr"
194  },
195  {
196    "MetricName": "l1_demand_data_cache_fills_from_near_memory_pti",
197    "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node per thousand instructions.",
198    "MetricExpr": "ls_dmnd_fills_from_sys.dram_io_near / instructions",
199    "MetricGroup": "l1_dcache",
200    "ScaleUnit": "1e3per_1k_instr"
201  },
202  {
203    "MetricName": "l1_demand_data_cache_fills_from_far_cache_pti",
204    "BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node per thousand instructions.",
205    "MetricExpr": "ls_dmnd_fills_from_sys.far_cache / instructions",
206    "MetricGroup": "l1_dcache",
207    "ScaleUnit": "1e3per_1k_instr"
208  },
209  {
210    "MetricName": "l1_demand_data_cache_fills_from_far_memory_pti",
211    "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node per thousand instructions.",
212    "MetricExpr": "ls_dmnd_fills_from_sys.dram_io_far / instructions",
213    "MetricGroup": "l1_dcache",
214    "ScaleUnit": "1e3per_1k_instr"
215  },
216  {
217    "MetricName": "l1_itlb_misses_pti",
218    "BriefDescription": "L1 instruction TLB misses per thousand instructions.",
219    "MetricExpr": "(bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all) / instructions",
220    "MetricGroup": "tlb",
221    "ScaleUnit": "1e3per_1k_instr"
222  },
223  {
224    "MetricName": "l2_itlb_misses_pti",
225    "BriefDescription": "L2 instruction TLB misses and instruction page walks per thousand instructions.",
226    "MetricExpr": "bp_l1_tlb_miss_l2_tlb_miss.all / instructions",
227    "MetricGroup": "tlb",
228    "ScaleUnit": "1e3per_1k_instr"
229  },
230  {
231    "MetricName": "l1_dtlb_misses_pti",
232    "BriefDescription": "L1 data TLB misses per thousand instructions.",
233    "MetricExpr": "ls_l1_d_tlb_miss.all / instructions",
234    "MetricGroup": "tlb",
235    "ScaleUnit": "1e3per_1k_instr"
236  },
237  {
238    "MetricName": "l2_dtlb_misses_pti",
239    "BriefDescription": "L2 data TLB misses and data page walks per thousand instructions.",
240    "MetricExpr": "ls_l1_d_tlb_miss.l2_miss_all / instructions",
241    "MetricGroup": "tlb",
242    "ScaleUnit": "1e3per_1k_instr"
243  },
244  {
245    "MetricName": "all_tlbs_flushed_pti",
246    "BriefDescription": "All TLBs flushed per thousand instructions.",
247    "MetricExpr": "ls_tlb_flush.all / instructions",
248    "MetricGroup": "tlb",
249    "ScaleUnit": "1e3per_1k_instr"
250  },
251  {
252    "MetricName": "macro_ops_dispatched",
253    "BriefDescription": "Macro-ops dispatched.",
254    "MetricExpr": "de_src_op_disp.all",
255    "MetricGroup": "decoder"
256  },
257  {
258    "MetricName": "sse_avx_stalls",
259    "BriefDescription": "Mixed SSE/AVX stalls.",
260    "MetricExpr": "fp_disp_faults.sse_avx_all"
261  },
262  {
263    "MetricName": "macro_ops_retired",
264    "BriefDescription": "Macro-ops retired.",
265    "MetricExpr": "ex_ret_ops"
266  },
267  {
268    "MetricName": "umc_data_bus_utilization",
269    "BriefDescription": "Memory controller data bus utilization.",
270    "MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)",
271    "MetricGroup": "memory_controller",
272    "PerPkg": "1",
273    "ScaleUnit": "100%"
274  },
275  {
276    "MetricName": "umc_cas_cmd_rate",
277    "BriefDescription": "Memory controller CAS command rate.",
278    "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
279    "MetricGroup": "memory_controller",
280    "PerPkg": "1",
281    "ScaleUnit": "1per_memclk"
282  },
283  {
284    "MetricName": "umc_cas_cmd_read_ratio",
285    "BriefDescription": "Ratio of memory controller CAS commands for reads.",
286    "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
287    "MetricGroup": "memory_controller",
288    "PerPkg": "1",
289    "ScaleUnit": "100%"
290  },
291  {
292    "MetricName": "umc_cas_cmd_write_ratio",
293    "BriefDescription": "Ratio of memory controller CAS commands for writes.",
294    "MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)",
295    "MetricGroup": "memory_controller",
296    "PerPkg": "1",
297    "ScaleUnit": "100%"
298  },
299  {
300    "MetricName": "umc_mem_read_bandwidth",
301    "BriefDescription": "Estimated memory read bandwidth.",
302    "MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time",
303    "MetricGroup": "memory_controller",
304    "PerPkg": "1",
305    "ScaleUnit": "1MB/s"
306  },
307  {
308    "MetricName": "umc_mem_write_bandwidth",
309    "BriefDescription": "Estimated memory write bandwidth.",
310    "MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time",
311    "MetricGroup": "memory_controller",
312    "PerPkg": "1",
313    "ScaleUnit": "1MB/s"
314  },
315  {
316    "MetricName": "umc_mem_bandwidth",
317    "BriefDescription": "Estimated combined memory bandwidth.",
318    "MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time",
319    "MetricGroup": "memory_controller",
320    "PerPkg": "1",
321    "ScaleUnit": "1MB/s"
322  },
323  {
324    "MetricName": "umc_activate_cmd_rate",
325    "BriefDescription": "Memory controller ACTIVATE command rate.",
326    "MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)",
327    "MetricGroup": "memory_controller",
328    "PerPkg": "1",
329    "ScaleUnit": "1per_memclk"
330  },
331  {
332    "MetricName": "umc_precharge_cmd_rate",
333    "BriefDescription": "Memory controller PRECHARGE command rate.",
334    "MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)",
335    "MetricGroup": "memory_controller",
336    "PerPkg": "1",
337    "ScaleUnit": "1per_memclk"
338  }
339]
340