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/linux/include/dt-bindings/pinctrl/
H A Dk210-fpioa.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 * kendryte-standalone-sdk/lib/drivers/include/fpioa.h
32 #define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */
33 #define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */
38 #define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */
39 #define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */
40 #define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */
41 #define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */
42 #define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */
43 #define K210_PCF_GPIOHS5 29 /* GPIO High speed 5 */
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/linux/Documentation/hwmon/
H A Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
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H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
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H A Daquacomputer_d5next.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver aquacomputer-d5next
14 * Aquacomputer High Flow Next sensor
19 * Aquacomputer High Flow USB flow meter
25 -----------
32 speed (in RPM), power, voltage and current. Temperature offsets and fan speeds
35 For the D5 Next pump, available sensors are pump and fan speed, power, voltage
37 available through debugfs are the serial number, firmware version and power-on
39 temperature curves directly from the pump. If it's not connected, the fan-related
49 as well as eight PWM controllable fans, along with their speed (in RPM), power, voltage
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H A Dw83792d.rst10 Addresses scanned: I2C 0x2c - 0x2f
19 -----------------
35 -----------
42 parameter; this will put it into a more well-behaved state first.
44 The driver implements three temperature sensors, seven fan rotation speed
48 The driver also implements up to seven fan control outputs: pwm1-7. Pwm1-7
53 Automatic fan control mode is possible only for fan1-fan3.
55 For all pwmX outputs, a value of 0 means minimum fan speed and a value of
56 255 means maximum fan speed.
64 triggered if the rotation speed has dropped below a programmable limit. Fan
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H A Df71805f.rst44 -----------
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
89 in6 VIN6 VCC1.5V 10K - 1.00 1.50 V
90 in7 VIN7 VCORE 10K - 1.00 ~1.40 V [1]_
106 Each voltage measured has associated low and high limits, each of which
111 --------------
113 Fan rotation speeds are reported as 12-bit values from a gated clock
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H A Dadm1026.rst16 - Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
17 - Justin Thiessen <jthiessen@penguincomputing.com>
20 -----------------
23 List of GPIO pins (0-16) to program as inputs
26 List of GPIO pins (0-16) to program as outputs
29 List of GPIO pins (0-16) to program as inverted
32 List of GPIO pins (0-16) to program as normal/non-inverted
35 List of GPIO pins (0-7) to program as fan tachs
39 -----------
45 16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit),
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-pci-drivers-ehci_hcd7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
9 "companion" full/low-speed USB-1.1 controllers. When a
10 high-speed device is plugged in, the connection is routed
11 to the EHCI controller; when a full- or low-speed device
15 Sometimes you want to force a high-speed device to connect
16 at full speed, which can be accomplished by forcing the
23 For example: To force the high-speed device attached to
24 port 4 on bus 2 to run at full speed::
28 To return the port to high-speed operation::
30 echo -4 >/sys/bus/usb/devices/usb2/../companion
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/linux/Documentation/usb/
H A Dehci.rst5 27-Dec-2002
7 The EHCI driver is used to talk to high speed USB 2.0 devices using
8 USB 2.0-capable host controller hardware. The USB 2.0 standard is
11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
15 USB 1.1 only addressed full speed and low speed. High speed devices
23 (TT) in the hub, which turns low or full speed transactions into
24 high speed "split transactions" that don't waste transfer bandwidth.
31 While usb-storage devices have been available since mid-2001 (working
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/linux/drivers/usb/gadget/function/
H A Du_uvc.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
36 * Control descriptors array pointers for full-/high-speed and
37 * super-speed. They point by default to the uvc_fs_control_cls and
45 * Streaming descriptors array pointers for full-speed, high-speed and
46 * super-speed. They will point to the uvc_[fhs]s_streaming_cls arrays
47 * for configfs-based gadgets. Legacy gadgets must initialize them in
54 /* Default control descriptors for configfs-based gadgets. */
60 * Control descriptors pointers arrays for full-/high-speed and
61 * super-speed. The first element is a configurable control header
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/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
87 multi-lane QMP block that can be configured either as one wide
134 controllers on Qualcomm chips. This driver supports the high-speed
143 Enable support for the USB high-speed eUSB2 repeater on Qualcomm
184 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
187 Support for the USB high-speed ULPI compliant phy on Qualcomm
195 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
208 tristate "Qualcomm 28nm High-Speed PHY"
210 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
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/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
34 cd-gpios:
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/linux/Documentation/devicetree/bindings/usb/
H A Dusb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
38 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
40 serial is specified and High-Speed Inter-Chip feature if HSIC is
46 maximum-speed:
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/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dhsta.txt2 ppc476gtr High Speed Serial Assist (HSTA) node
5 The 476gtr SoC contains a high speed serial assist module attached
6 between the plb4 and plb6 system buses to provide high speed data
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
/linux/drivers/infiniband/hw/hfi1/
H A Dmad.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright(c) 2015 - 2017 Intel Corporation.
41 #define OPA_NOTICE_TRAP_LSE_CHG 0x04 /* Link Speed Enable changed */
101 u8 sl; /* SL: high 5 bits */
105 __be32 qp1; /* high 8 bits reserved */
106 __be32 qp2; /* high 8 bits reserved */
114 u8 sl; /* SL: high 5 bits */
118 __be32 qp1; /* high 8 bits reserved */
119 __be32 qp2; /* high 8 bits reserved */
299 * struct cc_state combines the (active) per-port congestion control
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/linux/drivers/usb/dwc2/
H A Dhcd.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hcd.h - DesignWare HS OTG Controller host-mode declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
24 * struct dwc2_host_chan - Software host channel descriptor
30 * @speed: Device speed. One of the following values:
31 * - USB_SPEED_LOW
32 * - USB_SPEED_FULL
33 * - USB_SPEED_HIGH
35 * - USB_ENDPOINT_XFER_CONTROL: 0
36 * - USB_ENDPOINT_XFER_ISOC: 1
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H A Dhcd_queue.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
17 #include <linux/dma-mapping.h>
36 * dwc2_periodic_channel_available() - Checks that a channel is available for a
48 * non-periodic transactions in dwc2_periodic_channel_available()
53 num_channels = hsotg->params.host_channels; in dwc2_periodic_channel_available()
54 if ((hsotg->periodic_channels + hsotg->non_periodic_channels < in dwc2_periodic_channel_available()
55 num_channels) && (hsotg->periodic_channels < num_channels - 1)) { in dwc2_periodic_channel_available()
58 dev_dbg(hsotg->dev, in dwc2_periodic_channel_available()
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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_cyclone5_chameleon96.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
28 compatible = "regulator-fixed";
29 regulator-name = "3.3V";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
35 compatible = "gpio-leds";
40 linux,default-trigger = "heartbeat";
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
22 pin configuration parameters, such as pull-up, tristate, drive strength,
46 $ref: /schemas/types.yaml#/definitions/string-array
57 description: Pull-down/up setting to apply to the pin.
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/linux/drivers/message/fusion/
H A Dmptfc.c6 * Copyright (c) 1999-2008 LSI Corporation
7 * (mailto:DL-MPTFusionLinux@lsi.com)
10 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
24 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
43 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
69 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
88 /* scsi-mid layer global parmeter is max_report_luns, which is 511 */
129 .this_id = -1,
198 ioc = hd->ioc; in mptfc_block_error_handler()
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/linux/Documentation/devicetree/bindings/phy/
H A Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
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/linux/Documentation/devicetree/bindings/net/
H A Deswin,eic7700-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shuang Liang <liangshuang@eswincomputing.com>
11 - Zhi Li <lizhi2@eswincomputing.com>
12 - Shangjuan Wei <weishangjuan@eswincomputing.com>
22 - eswin,eic7700-qos-eth
23 - eswin,eic7700-qos-eth-clk-inversion
25 - compatible
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/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32mp21-rcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
17 include/dt-bindings/clock/st,stm32mp21-rcc.h
18 include/dt-bindings/reset/st,stm32mp21-rcc.h
23 - st,stm32mp21-rcc
28 '#clock-cells':
31 '#reset-cells':
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/linux/drivers/usb/musb/
H A Dmusb_debugfs.c1 // SPDX-License-Identifier: GPL-2.0
86 struct musb *musb = s->private; in musb_regdump_show()
90 pm_runtime_get_sync(musb->controller); in musb_regdump_show()
95 seq_printf(s, "%-12s: %02x\n", musb_regmap[i].name, in musb_regdump_show()
96 musb_readb(musb->mregs, musb_regmap[i].offset)); in musb_regdump_show()
99 seq_printf(s, "%-12s: %04x\n", musb_regmap[i].name, in musb_regdump_show()
100 musb_readw(musb->mregs, musb_regmap[i].offset)); in musb_regdump_show()
103 seq_printf(s, "%-12s: %08x\n", musb_regmap[i].name, in musb_regdump_show()
104 musb_readl(musb->mregs, musb_regmap[i].offset)); in musb_regdump_show()
109 pm_runtime_put_autosuspend(musb->controller); in musb_regdump_show()
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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_thermal.c38 return -EINVAL); in vega12_get_current_rpm()
47 fan_speed_info->supports_percent_read = false; in vega12_fan_ctrl_get_fan_speed_info()
48 fan_speed_info->supports_percent_write = false; in vega12_fan_ctrl_get_fan_speed_info()
49 fan_speed_info->supports_rpm_read = true; in vega12_fan_ctrl_get_fan_speed_info()
50 fan_speed_info->supports_rpm_write = true; in vega12_fan_ctrl_get_fan_speed_info()
55 int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) in vega12_fan_ctrl_get_fan_speed_rpm() argument
57 *speed = 0; in vega12_fan_ctrl_get_fan_speed_rpm()
59 return vega12_get_current_rpm(hwmgr, speed); in vega12_fan_ctrl_get_fan_speed_rpm()
63 * vega12_enable_fan_control_feature -Enables the SMC Fan Control Feature.
66 * Return: 0 on success. -1 otherwise.
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