Home
last modified time | relevance | path

Searched +full:hdmi +full:- +full:tx (Results 1 – 25 of 297) sorted by relevance

12345678910>>...12

/linux/Documentation/devicetree/bindings/display/msm/
H A Dhdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/display/msm/hdmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon HDMI output
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-tx-8084
17 - qcom,hdmi-tx-8660
18 - qcom,hdmi-tx-8960
19 - qcom,hdmi-tx-8974
[all …]
H A Dqcom,mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Damlogic,meson8-hdmi-tx-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 The HDMI TX PHY node should be the child of a syscon node with the
16 compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
23 pattern: "^hdmi-phy@[0-9a-f]+$"
27 - items:
[all …]
H A Dmediatek,hdmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car DWC HDMI TX Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: synopsys,dw-hdmi.yaml#
22 - enum:
23 - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
[all …]
H A Dfsl,imx8mp-hdmi-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8MP DWC HDMI TX Encoder
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HDMI transmitter is a Synopsys DesignWare
14 HDMI 2.0a TX controller IP.
17 - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
22 - fsl,imx8mp-hdmi-tx
[all …]
H A Dsynopsys,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Synopsys DesignWare HDMI TX Controller
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This document defines device tree properties for the Synopsys DesignWare HDMI
14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
26 reg-io-width:
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 HDMI Controller
10 The HDMI Encoder supports the HDMI video and audio outputs, and does
14 - Chen-Yu Tsai <wens@csie.org>
15 - Maxime Ripard <mripard@kernel.org>
20 - const: allwinner,sun4i-a10-hdmi
21 - const: allwinner,sun5i-a10s-hdmi
[all …]
H A Dallwinner,sun8i-a83t-dw-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
19 - Chen-Yu Tsai <wens@csie.org>
20 - Maxime Ripard <mripard@kernel.org>
[all …]
H A Dbrcm,bcm2711-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM2711 HDMI Controller
10 - Eric Anholt <eric@anholt.net>
15 - brcm,bcm2711-hdmi0
16 - brcm,bcm2711-hdmi1
20 - description: HDMI controller register range
21 - description: DVP register range
[all …]
H A Damlogic,meson-dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 - $ref: /schemas/sound/dai-common.yaml#
18 - A Synopsys DesignWare HDMI Controller IP
19 - A TOP control block controlling the Clocks and PHY
20 - A custom HDMI PHY in order to convert video to TMDS signal
[all …]
H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
[all …]
/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <sound/hdmi-codec.h>
17 #include "hdmi.h"
19 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on) in msm_hdmi_set_mode() argument
24 spin_lock_irqsave(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
27 if (!hdmi->hdmi_mode) { in msm_hdmi_set_mode()
29 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
38 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
39 spin_unlock_irqrestore(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
40 DBG("HDMI Core: %s, HDMI_CTRL=0x%08x", in msm_hdmi_set_mode()
[all …]
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hdmi-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HDMI blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
15 peripherals located in the HDMI domain of the SoC.
20 - const: fsl,imx8mp-hdmi-blk-ctrl
21 - const: syscon
[all …]
/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DWC HDMI TX Encoder
10 - Mark Yao <markyao0591@gmail.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
18 - $ref: /schemas/sound/dai-common.yaml#
23 - rockchip,rk3228-dw-hdmi
[all …]
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8mp-hdmi-tx.c1 // SPDX-License-Identifier: GPL-2.0+
25 struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data; in imx8mp_hdmi_mode_valid() local
28 if (mode->clock < 13500) in imx8mp_hdmi_mode_valid()
31 if (mode->clock > 297000) in imx8mp_hdmi_mode_valid()
34 round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000); in imx8mp_hdmi_mode_valid()
35 /* imx8mp's pixel clock generator (fsl-samsung-hdmi) cannot generate in imx8mp_hdmi_mode_valid()
39 * 0.5% = 5/1000 tolerance (mode->clock is 1/1000) in imx8mp_hdmi_mode_valid()
41 if (abs(round_rate - mode->clock * 1000) > mode->clock * 5) in imx8mp_hdmi_mode_valid()
44 /* We don't support double-clocked and Interlaced modes */ in imx8mp_hdmi_mode_valid()
45 if ((mode->flags & DRM_MODE_FLAG_DBLCLK) || in imx8mp_hdmi_mode_valid()
[all …]
/linux/drivers/media/i2c/adv748x/
H A Dadv748x-csi2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Analog Devices ADV748X CSI-2 Transmitter
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-ioctl.h>
25 int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc) in adv748x_csi2_set_virtual_channel() argument
27 return tx_write(tx, ADV748X_CSI_VC_REF, vc << ADV748X_CSI_VC_REF_SHIFT); in adv748x_csi2_set_virtual_channel()
33 * @tx: CSI2 private entity
36 * @src_pad: Pad number of source to link to this @tx
42 static int adv748x_csi2_register_link(struct adv748x_csi2 *tx, in adv748x_csi2_register_link() argument
[all …]
H A Dadv748x-core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Analog Devices ADV748X HDMI receiver with AFE
21 #include <linux/v4l2-dv-timings.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-dv-timings.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-ioctl.h>
31 /* -----------------------------------------------------------------------------
48 ADV748X_REGMAP_CONF("hdmi"),
[all …]
H A Dadv748x-hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Analog Devices ADV748X HDMI receiver and Component Processor (CP)
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-dv-timings.h>
14 #include <media/v4l2-ioctl.h>
16 #include <uapi/linux/v4l2-dv-timings.h>
20 /* -----------------------------------------------------------------------------
21 * HDMI and CP
29 /* V4L2_DV_BT_CEA_720X480I59_94 - 0.5 MHz */
[all …]
/linux/sound/soc/fsl/
H A Dimx-hdmi.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2017-2020 NXP
8 #include <sound/hdmi-codec.h>
12 * struct cpu_priv - CPU private data
16 * Note: [1] for tx and [0] for rx
36 struct imx_hdmi_data *data = snd_soc_card_get_drvdata(rtd->card); in imx_hdmi_hw_params()
37 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in imx_hdmi_hw_params() local
39 struct snd_soc_card *card = rtd->card; in imx_hdmi_hw_params()
40 struct device *dev = card->dev; in imx_hdmi_hw_params()
41 u32 slot_width = data->cpu_priv.slot_width; in imx_hdmi_hw_params()
[all …]
/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx6-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 DWC HDMI TX Encoder
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - fsl,imx6dl-hdmi
23 - fsl,imx6q-hdmi
[all …]
H A Dfsl,imx8mp-hdmi-pvi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8MP HDMI Parallel Video Interface
10 - Lucas Stach <l.stach@pengutronix.de>
13 The HDMI parallel video interface is a timing and sync generator block in the
14 i.MX8MP SoC, that sits between the video source and the HDMI TX controller.
18 const: fsl,imx8mp-hdmi-pvi
26 power-domains:
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
25 static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read) in fifo_transfer() argument
41 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
45 * For TX the threshold is for an empty FIFO. in fifo_transfer()
50 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
53 return -ETIMEDOUT; in fifo_transfer()
56 return -EIO; in fifo_transfer()
59 ioread8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
61 iowrite8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/sound/meson-aiu.h>
15 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
16 model = "Hardkernel ODROID-C2";
24 stdout-path = "serial0:115200n8";
32 usb_otg_pwr: regulator-usb-pwrs {
33 compatible = "regulator-fixed";
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-boneblack.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "am335x-bone-common.dtsi"
9 #include "am335x-boneblack-common.dtsi"
10 #include "am335x-boneblack-hdmi.dtsi"
14 compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
23 opp-1000000000 {
25 opp-supported-hw = <0x06 0x0100>;
30 gpio-line-names =
[all …]

12345678910>>...12