Lines Matching +full:hdmi +full:- +full:tx
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
21 pattern: "^hdmi-phy@[0-9a-f]+$"
25 - items:
26 - enum:
27 - mediatek,mt7623-hdmi-phy
28 - const: mediatek,mt2701-hdmi-phy
29 - const: mediatek,mt2701-hdmi-phy
30 - const: mediatek,mt8173-hdmi-phy
31 - const: mediatek,mt8195-hdmi-phy
38 - description: PLL reference clock
40 clock-names:
42 - const: pll_ref
44 clock-output-names:
46 - const: hdmitx_dig_cts
48 "#phy-cells":
51 "#clock-cells":
56 TX DRV bias current for < 1.65Gbps
64 TX DRV bias current for >= 1.65Gbps
71 - compatible
72 - reg
73 - clocks
74 - clock-names
75 - clock-output-names
76 - "#phy-cells"
77 - "#clock-cells"
82 - |
83 #include <dt-bindings/clock/mt8173-clk.h>
84 hdmi_phy: hdmi-phy@10209100 {
85 compatible = "mediatek,mt8173-hdmi-phy";
88 clock-names = "pll_ref";
89 clock-output-names = "hdmitx_dig_cts";
92 #clock-cells = <0>;
93 #phy-cells = <0>;