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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq5424-apss-clk.yaml27 - description: Reference to the GPLL0 clock.
52 <&gcc GPLL0>;
H A Dqcom,gpucc-sdm660.yaml27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
H A Dqcom,qcm2290-gpucc.yaml32 - description: GPLL0 main branch source
33 - description: GPLL0 div branch source
H A Dqcom,qcm2290-dispcc.yaml32 - description: GPLL0 source from GCC
33 - description: GPLL0 div source from GCC
H A Dqcom,sm8450-gpucc.yaml53 - description: GPLL0 main branch source
54 - description: GPLL0 div branch source
/linux/drivers/clk/qcom/
H A Dgcc-sc7180.c35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
68 &gpll0.clkr.hw,
81 &gpll0.clkr.hw,
168 { .hw = &gpll0.clkr.hw },
174 { .hw = &gpll0.clkr.hw },
187 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
215 { .hw = &gpll0.clkr.hw },
227 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm7150.c40 static struct clk_alpha_pll gpll0 = { variable
47 .name = "gpll0",
75 &gpll0.clkr.hw,
88 &gpll0.clkr.hw,
137 { .hw = &gpll0.clkr.hw },
142 { .hw = &gpll0.clkr.hw },
155 { .hw = &gpll0.clkr.hw },
167 { .hw = &gpll0.clkr.hw },
172 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-qcm2290.c57 static struct clk_alpha_pll gpll0 = { variable
64 .name = "gpll0",
88 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
416 { .hw = &gpll0.clkr.hw },
429 { .hw = &gpll0.clkr.hw },
443 { .hw = &gpll0.clkr.hw },
459 { .hw = &gpll0.clkr.hw },
477 { .hw = &gpll0.clkr.hw },
494 { .hw = &gpll0.clkr.hw },
512 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-qcs615.c43 static struct clk_alpha_pll gpll0 = { variable
50 .name = "gpll0",
60 /* Fixed divider clock of GPLL0 instead of PLL normal postdiv */
67 .hw = &gpll0.clkr.hw,
225 { .hw = &gpll0.clkr.hw },
231 { .hw = &gpll0.clkr.hw },
232 { .hw = &gpll0.clkr.hw },
244 { .hw = &gpll0.clkr.hw },
258 { .hw = &gpll0.clkr.hw },
291 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6115.c57 static struct clk_alpha_pll gpll0 = { variable
66 .name = "gpll0",
90 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
110 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
475 { .hw = &gpll0.clkr.hw },
488 { .hw = &gpll0.clkr.hw },
502 { .hw = &gpll0.clkr.hw },
517 { .hw = &gpll0.clkr.hw },
532 { .hw = &gpll0.clkr.hw },
548 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6375.c61 static struct clk_alpha_pll gpll0 = { variable
68 .name = "gpll0",
93 &gpll0.clkr.hw,
115 &gpll0.clkr.hw,
447 { .hw = &gpll0.clkr.hw },
460 { .hw = &gpll0.clkr.hw },
474 { .hw = &gpll0.clkr.hw },
481 { .hw = &gpll0.clkr.hw },
497 { .hw = &gpll0.clkr.hw },
515 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sdx55.c36 static struct clk_alpha_pll gpll0 = { variable
45 .name = "gpll0",
73 &gpll0.clkr.hw,
143 { .hw = &gpll0.clkr.hw },
149 { .hw = &gpll0.clkr.hw },
163 { .hw = &gpll0.clkr.hw },
178 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
1556 [GPLL0] = &gpll0.clkr,
H A Dgcc-sm6350.c34 static struct clk_alpha_pll gpll0 = { variable
41 .name = "gpll0",
66 &gpll0.clkr.hw,
88 &gpll0.clkr.hw,
160 { .hw = &gpll0.clkr.hw },
201 { .hw = &gpll0.clkr.hw },
260 &gpll0.clkr.hw,
274 &gpll0.clkr.hw,
1163 &gpll0.clkr.hw,
1277 &gpll0.clkr.hw,
[all …]
H A Dmmcc-msm8996.c50 { .fw_name = "gpll0", .name = "gpll0" },
352 { .fw_name = "gpll0", .name = "gpll0" },
378 { .fw_name = "gpll0", .name = "gpll0" },
394 { .fw_name = "gpll0", .name = "gpll0" },
410 { .fw_name = "gpll0", .name = "gpll0" },
426 { .fw_name = "gpll0", .name = "gpll0" },
442 { .fw_name = "gpll0", .name = "gpll0" },
461 { .fw_name = "gpll0", .name = "gpll0" },
480 { .fw_name = "gpll0", .name = "gpll0" },
500 { .fw_name = "gpll0", .name = "gpll0" },
H A Dgcc-ipq5018.c120 static struct clk_alpha_pll_postdiv gpll0 = { variable
125 .name = "gpll0",
193 { .hw = &gpll0.clkr.hw },
205 { .hw = &gpll0.clkr.hw },
216 { .hw = &gpll0.clkr.hw },
228 { .hw = &gpll0.clkr.hw },
239 { .hw = &gpll0.clkr.hw },
251 { .hw = &gpll0.clkr.hw },
265 { .hw = &gpll0.clkr.hw },
277 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-ipq5332.c78 static struct clk_alpha_pll_postdiv gpll0 = { variable
83 .name = "gpll0",
159 { .hw = &gpll0.clkr.hw },
170 { .hw = &gpll0.clkr.hw },
181 { .hw = &gpll0.clkr.hw },
194 { .hw = &gpll0.clkr.hw },
209 { .hw = &gpll0.clkr.hw },
222 { .hw = &gpll0.clkr.hw },
223 { .hw = &gpll0.clkr.hw },
237 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-ipq5424.c54 static struct clk_alpha_pll gpll0 = { variable
61 .name = "gpll0",
75 &gpll0.clkr.hw
89 &gpll0.clkr.hw
158 { .hw = &gpll0.clkr.hw },
169 { .hw = &gpll0.clkr.hw },
180 { .hw = &gpll0.clkr.hw },
194 { .hw = &gpll0.clkr.hw },
216 { .hw = &gpll0.clkr.hw },
237 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sdx65.c35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
66 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
80 { .hw = &gpll0.clkr.hw },
86 { .hw = &gpll0.clkr.hw },
99 { .hw = &gpll0.clkr.hw },
1511 [GPLL0] = &gpll0.clkr,
H A Dgcc-sdm660.c80 static struct clk_alpha_pll_postdiv gpll0 = { variable
84 .name = "gpll0",
175 { .hw = &gpll0.clkr.hw },
186 { .hw = &gpll0.clkr.hw },
198 { .hw = &gpll0.clkr.hw },
234 { .hw = &gpll0.clkr.hw },
250 { .hw = &gpll0.clkr.hw },
264 { .hw = &gpll0.clkr.hw },
1603 &gpll0.clkr.hw,
1669 &gpll0.clkr.hw,
[all …]
H A Dgcc-shikra.c78 static struct clk_alpha_pll gpll0 = { variable
85 .name = "gpll0",
110 &gpll0.clkr.hw,
473 { .hw = &gpll0.clkr.hw },
486 { .hw = &gpll0.clkr.hw },
500 { .hw = &gpll0.clkr.hw },
516 { .hw = &gpll0.clkr.hw },
544 { .hw = &gpll0.clkr.hw },
561 { .hw = &gpll0.clkr.hw },
579 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-ipq9650.c78 static struct clk_alpha_pll_postdiv gpll0 = { variable
83 .name = "gpll0",
166 { .hw = &gpll0.clkr.hw },
178 { .hw = &gpll0.clkr.hw },
189 { .hw = &gpll0.clkr.hw },
210 { .hw = &gpll0.clkr.hw },
222 { .hw = &gpll0.clkr.hw },
236 { .hw = &gpll0.clkr.hw },
250 { .hw = &gpll0.clkr.hw },
263 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-mdm9607.c53 static struct clk_alpha_pll_postdiv gpll0 = { variable
58 .name = "gpll0",
72 { .hw = &gpll0.clkr.hw },
113 { .hw = &gpll0.clkr.hw },
156 { .hw = &gpll0.clkr.hw },
1313 [GPLL0] = &gpll0.clkr,
/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom,apcs-kpss-global.yaml175 - description: GCC GPLL0 clock source
180 - const: gpll0
/linux/include/dt-bindings/clock/
H A Dqcom,gcc-mdm9607.h9 #define GPLL0 0 macro
H A Dqcom,gcc-sdx55.h10 #define GPLL0 3 macro

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