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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,msm8998-gpucc.yaml25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
30 - const: gpll0
54 clock-names = "xo", "gpll0";
H A Dqcom,sm6115-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 main div source
H A Dqcom,gpucc-sdm660.yaml27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
H A Dqcom,qcm2290-gpucc.yaml30 - description: GPLL0 main branch source
31 - description: GPLL0 div branch source
H A Dqcom,qcm2290-dispcc.yaml26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
H A Dqcom,sm6375-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 div branch source
H A Dqcom,sdm845-dispcc.yaml28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
H A Dqcom,gpucc.yaml47 - description: GPLL0 main branch source
48 - description: GPLL0 div branch source
H A Dqcom,sm6115-dispcc.yaml29 - description: GPLL0 DISP DIV clock from GCC
H A Dqcom,sm6125-gpucc.yaml26 - description: GPLL0 main branch source
H A Dqcom,sm6375-dispcc.yaml28 - description: GPLL0 source from GCC
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,osm-l3.yaml67 #define GPLL0 165
74 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
/linux/drivers/clk/qcom/
H A Dgcc-sc7180.c35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
68 &gpll0.clkr.hw,
81 &gpll0.clkr.hw,
168 { .hw = &gpll0.clkr.hw },
174 { .hw = &gpll0.clkr.hw },
187 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
215 { .hw = &gpll0.clkr.hw },
227 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-qcm2290.c57 static struct clk_alpha_pll gpll0 = { variable
64 .name = "gpll0",
88 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
416 { .hw = &gpll0.clkr.hw },
429 { .hw = &gpll0.clkr.hw },
443 { .hw = &gpll0.clkr.hw },
459 { .hw = &gpll0.clkr.hw },
477 { .hw = &gpll0.clkr.hw },
494 { .hw = &gpll0.clkr.hw },
512 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm7150.c41 static struct clk_alpha_pll gpll0 = { variable
48 .name = "gpll0",
76 &gpll0.clkr.hw,
89 &gpll0.clkr.hw,
138 { .hw = &gpll0.clkr.hw },
143 { .hw = &gpll0.clkr.hw },
156 { .hw = &gpll0.clkr.hw },
168 { .hw = &gpll0.clkr.hw },
173 { .hw = &gpll0.clkr.hw },
203 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6115.c57 static struct clk_alpha_pll gpll0 = { variable
66 .name = "gpll0",
90 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
110 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
475 { .hw = &gpll0.clkr.hw },
488 { .hw = &gpll0.clkr.hw },
502 { .hw = &gpll0.clkr.hw },
517 { .hw = &gpll0.clkr.hw },
532 { .hw = &gpll0.clkr.hw },
548 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6375.c61 static struct clk_alpha_pll gpll0 = { variable
68 .name = "gpll0",
93 &gpll0.clkr.hw,
115 &gpll0.clkr.hw,
447 { .hw = &gpll0.clkr.hw },
460 { .hw = &gpll0.clkr.hw },
474 { .hw = &gpll0.clkr.hw },
481 { .hw = &gpll0.clkr.hw },
497 { .hw = &gpll0.clkr.hw },
515 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-ipq9574.c97 static struct clk_alpha_pll_postdiv gpll0 = { variable
102 .name = "gpll0",
186 { .hw = &gpll0.clkr.hw },
198 { .hw = &gpll0.clkr.hw },
208 { .hw = &gpll0.clkr.hw },
220 { .hw = &gpll0.clkr.hw },
222 { .hw = &gpll0.clkr.hw },
234 { .hw = &gpll0.clkr.hw },
248 { .hw = &gpll0.clkr.hw },
260 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sdx55.c36 static struct clk_alpha_pll gpll0 = { variable
45 .name = "gpll0",
73 &gpll0.clkr.hw,
143 { .hw = &gpll0.clkr.hw },
149 { .hw = &gpll0.clkr.hw },
163 { .hw = &gpll0.clkr.hw },
178 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
1556 [GPLL0] = &gpll0.clkr,
H A Dmmcc-msm8996.c53 { .fw_name = "gpll0", .name = "gpll0" },
355 { .fw_name = "gpll0", .name = "gpll0" },
381 { .fw_name = "gpll0", .name = "gpll0" },
397 { .fw_name = "gpll0", .name = "gpll0" },
413 { .fw_name = "gpll0", .name = "gpll0" },
429 { .fw_name = "gpll0", .name = "gpll0" },
445 { .fw_name = "gpll0", .name = "gpll0" },
464 { .fw_name = "gpll0", .name = "gpll0" },
483 { .fw_name = "gpll0", .name = "gpll0" },
503 { .fw_name = "gpll0", .name = "gpll0" },
H A Dgcc-msm8953.c69 static struct clk_alpha_pll_postdiv gpll0 = { variable
73 .name = "gpll0",
243 { .hw = &gpll0.clkr.hw },
255 { .hw = &gpll0.clkr.hw },
678 { .hw = &gpll0.clkr.hw },
748 { .hw = &gpll0.clkr.hw },
783 { .hw = &gpll0.clkr.hw },
849 { .hw = &gpll0.clkr.hw },
912 { .hw = &gpll0.clkr.hw },
1019 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-ipq5018.c121 static struct clk_alpha_pll_postdiv gpll0 = { variable
126 .name = "gpll0",
194 { .hw = &gpll0.clkr.hw },
206 { .hw = &gpll0.clkr.hw },
217 { .hw = &gpll0.clkr.hw },
229 { .hw = &gpll0.clkr.hw },
240 { .hw = &gpll0.clkr.hw },
252 { .hw = &gpll0.clkr.hw },
266 { .hw = &gpll0.clkr.hw },
278 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-ipq5332.c79 static struct clk_alpha_pll_postdiv gpll0 = { variable
84 .name = "gpll0",
160 { .hw = &gpll0.clkr.hw },
171 { .hw = &gpll0.clkr.hw },
182 { .hw = &gpll0.clkr.hw },
195 { .hw = &gpll0.clkr.hw },
210 { .hw = &gpll0.clkr.hw },
223 { .hw = &gpll0.clkr.hw },
224 { .hw = &gpll0.clkr.hw },
238 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sdx65.c35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
66 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
80 { .hw = &gpll0.clkr.hw },
86 { .hw = &gpll0.clkr.hw },
99 { .hw = &gpll0.clkr.hw },
1511 [GPLL0] = &gpll0.clkr,
H A Dgcc-sdm660.c80 static struct clk_alpha_pll_postdiv gpll0 = { variable
84 .name = "gpll0",
175 { .hw = &gpll0.clkr.hw },
186 { .hw = &gpll0.clkr.hw },
198 { .hw = &gpll0.clkr.hw },
234 { .hw = &gpll0.clkr.hw },
250 { .hw = &gpll0.clkr.hw },
264 { .hw = &gpll0.clkr.hw },
1603 &gpll0.clkr.hw,
1669 &gpll0.clkr.hw,
[all …]

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