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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq5424-apss-clk.yaml27 - description: Reference to the GPLL0 clock.
52 <&gcc GPLL0>;
H A Dqcom,gpucc-sdm660.yaml27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
H A Dqcom,qcm2290-gpucc.yaml30 - description: GPLL0 main branch source
31 - description: GPLL0 div branch source
H A Dqcom,gpucc.yaml47 - description: GPLL0 main branch source
48 - description: GPLL0 div branch source
H A Dqcom,ipq9574-nsscc.yaml30 - description: GCC GPLL0 OUT AUX clock source
/linux/drivers/clk/qcom/
H A Dgcc-sc7180.c35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
68 &gpll0.clkr.hw,
81 &gpll0.clkr.hw,
168 { .hw = &gpll0.clkr.hw },
174 { .hw = &gpll0.clkr.hw },
187 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
215 { .hw = &gpll0.clkr.hw },
227 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm7150.c41 static struct clk_alpha_pll gpll0 = { variable
48 .name = "gpll0",
76 &gpll0.clkr.hw,
89 &gpll0.clkr.hw,
138 { .hw = &gpll0.clkr.hw },
143 { .hw = &gpll0.clkr.hw },
156 { .hw = &gpll0.clkr.hw },
168 { .hw = &gpll0.clkr.hw },
173 { .hw = &gpll0.clkr.hw },
203 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6115.c57 static struct clk_alpha_pll gpll0 = { variable
66 .name = "gpll0",
90 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
110 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
475 { .hw = &gpll0.clkr.hw },
488 { .hw = &gpll0.clkr.hw },
502 { .hw = &gpll0.clkr.hw },
517 { .hw = &gpll0.clkr.hw },
532 { .hw = &gpll0.clkr.hw },
548 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6375.c61 static struct clk_alpha_pll gpll0 = { variable
68 .name = "gpll0",
93 &gpll0.clkr.hw,
115 &gpll0.clkr.hw,
447 { .hw = &gpll0.clkr.hw },
460 { .hw = &gpll0.clkr.hw },
474 { .hw = &gpll0.clkr.hw },
481 { .hw = &gpll0.clkr.hw },
497 { .hw = &gpll0.clkr.hw },
515 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6350.c34 static struct clk_alpha_pll gpll0 = { variable
41 .name = "gpll0",
66 &gpll0.clkr.hw,
88 &gpll0.clkr.hw,
160 { .hw = &gpll0.clkr.hw },
201 { .hw = &gpll0.clkr.hw },
260 &gpll0.clkr.hw,
274 &gpll0.clkr.hw,
1163 &gpll0.clkr.hw,
1277 &gpll0.clkr.hw,
[all …]
H A Dgcc-sdx55.c36 static struct clk_alpha_pll gpll0 = { variable
45 .name = "gpll0",
73 &gpll0.clkr.hw,
143 { .hw = &gpll0.clkr.hw },
149 { .hw = &gpll0.clkr.hw },
163 { .hw = &gpll0.clkr.hw },
178 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
1556 [GPLL0] = &gpll0.clkr,
H A Dgcc-ipq5332.c79 static struct clk_alpha_pll_postdiv gpll0 = { variable
84 .name = "gpll0",
160 { .hw = &gpll0.clkr.hw },
171 { .hw = &gpll0.clkr.hw },
182 { .hw = &gpll0.clkr.hw },
195 { .hw = &gpll0.clkr.hw },
210 { .hw = &gpll0.clkr.hw },
223 { .hw = &gpll0.clkr.hw },
224 { .hw = &gpll0.clkr.hw },
238 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sdx65.c35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
66 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
80 { .hw = &gpll0.clkr.hw },
86 { .hw = &gpll0.clkr.hw },
99 { .hw = &gpll0.clkr.hw },
1511 [GPLL0] = &gpll0.clkr,
H A Dgcc-sdm660.c80 static struct clk_alpha_pll_postdiv gpll0 = { variable
84 .name = "gpll0",
175 { .hw = &gpll0.clkr.hw },
186 { .hw = &gpll0.clkr.hw },
198 { .hw = &gpll0.clkr.hw },
234 { .hw = &gpll0.clkr.hw },
250 { .hw = &gpll0.clkr.hw },
264 { .hw = &gpll0.clkr.hw },
1603 &gpll0.clkr.hw,
1669 &gpll0.clkr.hw,
[all …]
H A Dgcc-ipq6018.c78 static struct clk_alpha_pll_postdiv gpll0 = { variable
83 .name = "gpll0",
93 { .hw = &gpll0.clkr.hw},
285 { .hw = &gpll0.clkr.hw },
364 { .hw = &gpll0.clkr.hw },
417 { .hw = &gpll0.clkr.hw },
468 { .hw = &gpll0.clkr.hw },
639 { .hw = &gpll0.clkr.hw },
673 { .hw = &gpll0.clkr.hw },
918 { .hw = &gpll0.clkr.hw },
[all …]
H A Dclk-cbf-8996.c279 /* Select GPLL0 for 300MHz for the CBF clock */ in qcom_msm8996_cbf_probe()
285 /* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */ in qcom_msm8996_cbf_probe()
H A Dgcc-sdx75.c66 static struct clk_alpha_pll gpll0 = { variable
73 .name = "gpll0",
98 &gpll0.clkr.hw,
181 { .hw = &gpll0.clkr.hw },
195 { .hw = &gpll0.clkr.hw },
210 { .hw = &gpll0.clkr.hw },
233 { .hw = &gpll0.clkr.hw },
336 { .hw = &gpll0.clkr.hw },
350 { .hw = &gpll0.clkr.hw },
2840 [GPLL0] = &gpll0.clkr,
H A Dgcc-sm8250.c35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
67 &gpll0.clkr.hw,
116 { .hw = &gpll0.clkr.hw },
122 { .hw = &gpll0.clkr.hw },
135 { .hw = &gpll0.clkr.hw },
168 { .hw = &gpll0.clkr.hw },
183 { .hw = &gpll0.clkr.hw },
1395 &gpll0.clkr.hw,
1535 &gpll0.clkr.hw,
[all …]
H A Dgcc-msm8909.c79 static struct clk_alpha_pll_postdiv gpll0 = { variable
83 .name = "gpll0",
189 { .hw = &gpll0.clkr.hw },
200 { .hw = &gpll0.clkr.hw },
651 { .hw = &gpll0.clkr.hw },
738 { .hw = &gpll0.clkr.hw },
784 { .hw = &gpll0.clkr.hw },
947 { .hw = &gpll0.clkr.hw },
2492 [GPLL0] = &gpll0.clkr,
H A Dapcs-msm8996.c55 * The sys_apcs_aux is a child (divider) of gpll0, but we register it in qcom_apcs_msm8996_clk_probe()
/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom,apcs-kpss-global.yaml173 - description: GCC GPLL0 clock source
178 - const: gpll0
/linux/include/dt-bindings/clock/
H A Dqcom,gcc-mdm9607.h9 #define GPLL0 0 macro
H A Dqcom,gcc-sdx55.h10 #define GPLL0 3 macro
H A Dqcom,gcc-sdx65.h10 #define GPLL0 0 macro
H A Dqcom,gcc-sc7180.h11 #define GPLL0 1 macro

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