| /freebsd/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | fpga-region.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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| H A D | fpga-region.txt | 1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Region
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| H A D | xlnx,fpga-selectmap.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx SelectMAP FPGA interface
10 - Charles Perry <charles.perry@savoirfairelinux.com>
22 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
27 - xlnx,fpga-xc7s-selectmap
28 - xlnx,fpga-xc7a-selectmap
29 - xlnx,fpga-xc7k-selectmap
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| H A D | xilinx-slave-serial.txt | 1 Xilinx Slave Serial SPI FPGA Manager
3 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
9 - https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
10 - https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
11 - https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
14 - compatible: should contain "xlnx,fpga-slave-serial"
15 - reg: spi chip select of the FPGA
16 - prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
17 - done-gpios: config status pin (referred to as DONE in the manual)
20 - init-b-gpios: initialization status and configuration error pin
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| H A D | xlnx,fpga-slave-serial.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Slave Serial SPI FPGA
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
24 - $ref: /schemas/spi/spi-peripheral-props.yaml#
29 - xlnx,fpga-slave-serial
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| H A D | microchip,mpf-spi-fpga-mgr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Polarfire FPGA manager.
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
19 - microchip,mpf-spi-fpga-mgr
23 maxItems: 1
26 - compatible
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| H A D | lattice,sysconfig.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/lattice,sysconfig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lattice Slave SPI sysCONFIG FPGA manager
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Lattice sysCONFIG port, which is used for FPGA configuration, among others,
18 format into FPGA's SRAM configuration memory.
23 - lattice,sysconfig-ecp5
26 maxItems: 1
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| H A D | altera-hps2fpga-bridge.txt | 1 Altera FPGA/HPS Bridge Driver
4 - regs : base address and size for AXI bridge module
5 - compatible : Should contain one of:
6 "altr,socfpga-lwhps2fpga-bridge",
7 "altr,socfpga-hps2fpga-bridge", or
8 "altr,socfpga-fpga2hps-bridge"
9 - resets : Phandle and reset specifier for this bridge's reset
10 - clocks : Clocks used by this module.
12 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
15 fpga_bridge0: fpga-bridge@ff400000 {
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| H A D | xlnx,pr-decoupler.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xln
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| /freebsd/sys/contrib/device-tree/Bindings/board/ |
| H A D | fsl,fpga-qixis.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale on-board FPGA/CPLD
10 - Frank Li <Frank.Li@nxp.com>
15 - items:
16 - const: fsl,p1022ds-fpga
17 - const: fsl,fpga-ngpixis
18 - items:
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| H A D | fsl,fpga-qixis-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale on-board FPGA connected on I2C bus
10 - Frank Li <Frank.Li@nxp.com>
15 - items:
16 - enum:
17 - fsl,bsc9132qds-fpga
18 - const: fsl,fpga-qixis-i2c
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| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | gef_ppc9a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
40 /* flash@0,0 is a mirror of part of the memory in flash@1,0
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| H A D | gef_sbc310.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
32 1 0 0xe0000000 0x08000000 // Paged Flash 0
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
35 4 0 0xfc000000 0x00010000>; // FPGA
37 /* flash@0,0 is a mirror of part of the memory in flash@1,0
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
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| H A D | ge_imp3a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
11 /include/ "p2020si-pre.dtsi"
33 /* nor@0,0 is a mirror of part of the memory in nor@1,0
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
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| H A D | gef_sbc610.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
40 /* flash@0,0 is a mirror of part of the memory in flash@1,0
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | ts-nbus.txt | 4 Systems FPGA on the TS-4600 SoM.
7 - compatible : "technologic,ts-nbus"
8 - #address-cells : must be 1
9 - #size-cells : must be 0
10 - pwms : The PWM bound to the FPGA
11 - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA
12 - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA
13 - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA
14 - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA
15 - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/ |
| H A D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | mdio-mux-mmioreg.txt | 1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
4 like an FPGA, is used to control which child bus is connected. The mdio-mux
5 node must be a child of the memory-mapped device. The driver currently only
6 supports devices with 8, 16 or 32-bit registers.
10 - compatible : string, must contain "mdio-mux-mmioreg"
12 - reg : integer, contains the offset of the register that controls the bus
14 register, and must therefore be 1, 2, or 4.
16 - mux-mask : integer, contains an eight-bit mask that specifies which
18 'reg' property of each child mdio-mux node must be constrained by
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | arm,versatile-fpga-irq.txt | 1 * ARM Versatile FPGA interrupt controller
3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
9 - compatible: "arm,versatile-fpga-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cell
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | cirrus,lochnagar.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
25 [1] GPIO : ../gpio/gpio.txt
26 [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt
29 [3] include/dt-bindings/pinctrl/lochnagar.h
37 - cirrus,lochnagar-pinctrl
39 gpio-controller: true
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| /freebsd/sys/contrib/device-tree/Bindings/ |
| H A D | xilinx.txt | 7 implemented within the fpga fabric every instance of the device can be
10 Each IP-core has a set of parameters which the FPGA designer can use to
15 to be recompiled every time the FPGA bitstream is resynthesized.
18 generate a new device tree each time the FPGA bitstream changes. The
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
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| /freebsd/sys/dev/mlx5/mlx5_fpga/ |
| H A D | mlx5fpga_core.c | 1 /*-
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
68 context, context->client); in client_context_destroy()
69 if (context->client->destroy) in client_context_destroy()
70 context->client->destroy(fdev); in client_context_destroy()
71 list_del(&context->list); in client_context_destroy()
83 return -ENOMEM; in client_context_create()
85 context->client = client; in client_context_create()
86 context->data = NULL; in client_context_create()
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| /freebsd/share/man/man4/man4.arm/ |
| H A D | devcfg.4 | 8 .\" 1. Redistributions of source code must retain the above copyright
36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
41 asserts the top-level PL reset signals, disables the PS-PL level shifters,
45 shifters and release the top-level PL reset signals.
47 The PL (FPGA) can be configured by writing the bitstream to the character
49 .Bd -literal -offset indent
53 The file should not be confused with the .bit file output by the FPGA
59 .Bd -literal -offset indent
60 promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
68 .Bl -tag -width 4n
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/4xx/ |
| H A D | akebono.txt | 11 - model : "ibm,akebono".
12 - compatible : "ibm,akebono" , "ibm,476gtr".
14 1.a) The Secure Digital Host Controller Interface (SDHCI) node
20 - compatible : should be "ibm,476gtr-sdhci","generic-sdhci".
21 - reg : should contain the SDHCI registers location and length.
22 - interrupts : should contain the SDHCI interrupt.
24 1.b) The Advanced Host Controller Interface (AHCI) SATA node
30 - compatible : should be "ibm,476gtr-ahci".
31 - reg : should contain the AHCI registers location and length.
32 - interrupts : should contain the AHCI interrupt.
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,juno-fpga-apb-regs.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,juno-fpga-apb-regs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Juno FPGA APB Registers
10 - Sudeep Holla <sudeep.holla@arm.com>
15 - const: arm,juno-fpga-apb-regs
16 - const: syscon
17 - const: simple-mfd
20 maxItems: 1
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