Lines Matching +full:fpga +full:- +full:1
8 .\" 1. Redistributions of source code must retain the above copyright
36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
41 asserts the top-level PL reset signals, disables the PS-PL level shifters,
45 shifters and release the top-level PL reset signals.
47 The PL (FPGA) can be configured by writing the bitstream to the character
49 .Bd -literal -offset indent
53 The file should not be confused with the .bit file output by the FPGA
59 .Bd -literal -offset indent
60 promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
68 .Bl -tag -width 4n
69 .It Va hw.fpga.pl_done
72 A 1 means the PL section has been properly programmed.
73 .It Va hw.fpga.en_level_shifters
75 This variable controls if the PS-PL level shifters are enabled after the
77 This variable is 1 by default but setting it to 0 allows the PL section to be
84 .Bl -tag -width 12n
91 Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585)