Lines Matching +full:fpga +full:- +full:1

1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer.  A memory-mapped device,
4 like an FPGA, is used to control which child bus is connected.  The mdio-mux
5 node must be a child of the memory-mapped device.  The driver currently only
6 supports devices with 8, 16 or 32-bit registers.
10 - compatible : string, must contain "mdio-mux-mmioreg"
12 - reg : integer, contains the offset of the register that controls the bus
14 	register, and must therefore be 1, 2, or 4.
16 - mux-mask : integer, contains an eight-bit mask that specifies which
18 	'reg' property of each child mdio-mux node must be constrained by
23 The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
25 A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on
28 	/* The FPGA node */
29 	fpga: board-control@3,0 {
30 		#address-cells = <1>;
31 		#size-cells = <1>;
32 		compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
36 		mdio-mux-emi2 {
37 			compatible = "mdio-mux-mmioreg", "mdio-mux";
38 			mdio-parent-bus = <&xmdio0>;
39 			#address-cells = <1>;
40 			#size-cells = <0>;
41 			reg = <9 1>; // BRDCFG1
42 			mux-mask = <0x6>; // EMI2
44 			emi2_slot1: mdio@0 {	// Slot 1 XAUI (FM2)
46 				#address-cells = <1>;
47 				#size-cells = <0>;
49 				phy_xgmii_slot1: ethernet-phy@0 {
50 					compatible = "ethernet-phy-ieee802.3-c45";
57 				#address-cells = <1>;
58 				#size-cells = <0>;
60 				phy_xgmii_slot2: ethernet-phy@4 {
61 					compatible = "ethernet-phy-ieee802.3-c45";
70 		#address-cells = <1>;
71 		#size-cells = <0>;
72 		compatible = "fsl,fman-xmdio";
74 		interrupts = <100 1 0 0>;