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/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
31 While ECAM extends this by 4 bits to accommodate 4k of function space:
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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H A Dpcie-al.txt3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
5 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
25 - "config" PCIe ECAM space
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/linux/drivers/pci/controller/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
63 Broadcom STB based SoCs, like the Raspberry Pi 4.
102 bool "Cavium Thunder PCIe controller to off-chip devices"
110 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
115 Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
149 in the Intel IXP4xx XScale-based network processor SoC.
185 is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370,
205 multi-function devices.
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H A Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
24 #include <linux/pci-ecam.h>
94 * struct xilinx_pcie - PCIe port information
115 return readl(pcie->reg_base + reg); in pcie_read()
120 writel(val, pcie->reg_base + reg); in pcie_write()
130 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
135 struct device *dev = pcie->dev; in xilinx_pcie_clear_err_interrupts()
147 * xilinx_pcie_valid_device - Check if a valid device is present on bus
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H A Dpci-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
19 #include <linux/pci-acpi.h>
20 #include <linux/pci-ecam.h>
74 return readl(port->csr_base + reg); in xgene_pcie_readl()
79 writel(val, port->csr_base + reg); in xgene_pcie_writel()
92 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
94 cfg = bus->sysdata; in pcie_bus_to_port()
95 return (struct xgene_pcie *)(cfg->priv); in pcie_bus_to_port()
106 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
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H A Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
159 * @imap_addr_offset: register offset between the upper and lower 32-bit
400 struct iproc_pcie *pcie = bus->sysdata; in iproc_data()
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/linux/arch/x86/pci/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Low-Level PCI Support for PC
5 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
10 #include <linux/pci-acpi.h>
35 int pcibios_last_bus = -1;
44 return raw_pci_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
46 return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
47 return -EINVAL; in raw_pci_read()
54 return raw_pci_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
56 return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/linux/drivers/net/ethernet/realtek/
H A Dr8169_main.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
26 #include <linux/dma-mapping.h>
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
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