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/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
31 While ECAM extends this by 4 bits to accommodate 4k of function space:
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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H A Damazon,al-alpine-v3-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/amazon,al-alpine-v3-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Chocron <jonnyc@amazon.com>
13 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys
17 - $ref: snps,dw-pcie.yaml#
22 - amazon,al-alpine-v2-pcie
23 - amazon,al-alpine-v3-pcie
27 - description: PCIe ECAM space
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/linux/drivers/pci/controller/
H A Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
15 #include <linux/irqchip/irq-msi-lib.h>
25 #include <linux/pci-ecam.h>
95 * struct xilinx_pcie - PCI
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H A Dpcie-xilinx-nwl.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
13 #include <linux/irqchip/irq-msi-lib.h>
22 #include <linux/pci-ecam.h>
35 /* Egress - Bridge translation registers */
45 /* Ingress - address translations */
53 /* Rxed msg fifo - Interrupt status registers */
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
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H A Dpci-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
73 return readl(port->csr_base + reg); in xgene_pcie_readl()
78 writel(val, port->csr_base + reg); in xgene_pcie_writel()
91 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
93 cfg = bus->sysdata; in pcie_bus_to_port()
94 return (struct xgene_pcie *)(cfg->priv); in pcie_bus_to_port()
105 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
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H A Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/irqchip/irq-msi-lib.h>
21 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
294 writel(val, pcie->base + reg); in advk_writel()
299 return readl(pcie->base + reg); in advk_readl()
314 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
322 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
336 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
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H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
26 #include <linux/irqchip/irq-msi-lib.h>
258 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
380 writel(value, pcie->af in afi_writel()
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/linux/arch/x86/pci/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Low-Level PCI Support for PC
5 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
10 #include <linux/pci-acpi.h>
35 int pcibios_last_bus = -1;
44 return raw_pci_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
46 return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
47 return -EINVAL; in raw_pci_read()
54 return raw_pci_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
56 return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/linux/drivers/net/ethernet/realtek/
H A Dr8169_main.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
26 #include <linux/dma-mapping.h>
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-
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