Lines Matching +full:ecam +full:- +full:based
1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
13 #include <linux/irqchip/irq-msi-lib.h>
22 #include <linux/pci-ecam.h>
35 /* Egress - Bridge translation registers */
45 /* Ingress - address translations */
53 /* Rxed msg fifo - Interrupt status registers */
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
202 struct device *dev = pcie->dev; in nwl_wait_for_link()
213 return -ETIMEDOUT; in nwl_wait_for_link()
218 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device()
232 * nwl_pcie_map_bus - Get configuration base
244 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus()
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in nwl_pcie_map_bus()
262 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
290 dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n"); in nwl_pcie_misc_handler()
299 dev_err_ratelimited(dev, "Non-Fatal Error Detected\n"); in nwl_pcie_misc_handler()
329 generic_handle_domain_irq(pcie->intx_irq_domain, bit); in nwl_pcie_leg_handler()
337 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
344 generic_handle_domain_irq(msi->dev_domain, bit); in nwl_pcie_handle_msi_irq()
376 mask = 1 << data->hwirq; in nwl_mask_intx_irq()
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
390 mask = 1 << data->hwirq; in nwl_unmask_intx_irq()
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
409 irq_set_chip_data(irq, domain->host_data); in nwl_intx_map()
433 .prefix = "nwl-",
442 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
444 msg->address_lo = lower_32_bits(msi_addr); in nwl_compose_msi_msg()
445 msg->address_hi = upper_32_bits(msi_addr); in nwl_compose_msi_msg()
446 msg->data = data->hwirq; in nwl_compose_msi_msg()
457 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc()
458 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
462 mutex_lock(&msi->lock); in nwl_irq_domain_alloc()
463 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, in nwl_irq_domain_alloc()
466 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
467 return -ENOSPC; in nwl_irq_domain_alloc()
472 domain->host_data, handle_simple_irq, in nwl_irq_domain_alloc()
475 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
484 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
486 mutex_lock(&msi->lock); in nwl_irq_domain_free()
487 bitmap_release_region(msi->bitmap, data->hwirq, in nwl_irq_domain_free()
489 mutex_unlock(&msi->lock); in nwl_irq_domain_free()
500 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
501 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
509 msi->dev_domain = msi_create_parent_irq_domain(&info, &nwl_msi_parent_ops); in nwl_pcie_init_msi_irq_domain()
510 if (!msi->dev_domain) { in nwl_pcie_init_msi_irq_domain()
512 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
520 int err = phy_power_off(pcie->phy[i]); in nwl_pcie_phy_power_off()
523 dev_err(pcie->dev, "could not power off phy %d (err=%d)\n", i, in nwl_pcie_phy_power_off()
529 int err = phy_exit(pcie->phy[i]); in nwl_pcie_phy_exit()
532 dev_err(pcie->dev, "could not exit phy %d (err=%d)\n", i, err); in nwl_pcie_phy_exit()
539 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { in nwl_pcie_phy_enable()
540 ret = phy_init(pcie->phy[i]); in nwl_pcie_phy_enable()
544 ret = phy_power_on(pcie->phy[i]); in nwl_pcie_phy_enable()
554 while (i--) { in nwl_pcie_phy_enable()
566 for (i = ARRAY_SIZE(pcie->phy); i--;) { in nwl_pcie_phy_disable()
574 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
575 struct device_node *node = dev->of_node; in nwl_pcie_init_irq_domain()
581 return -EINVAL; in nwl_pcie_init_irq_domain()
584 pcie->intx_irq_domain = irq_domain_create_linear(of_fwnode_handle(intc_node), PCI_NUM_INTX, in nwl_pcie_init_irq_domain()
587 if (!pcie->intx_irq_domain) { in nwl_pcie_init_irq_domain()
589 return -ENOMEM; in nwl_pcie_init_irq_domain()
592 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
599 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
601 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
605 mutex_init(&msi->lock); in nwl_pcie_enable_msi()
608 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in nwl_pcie_enable_msi()
609 if (msi->irq_msi1 < 0) in nwl_pcie_enable_msi()
610 return -EINVAL; in nwl_pcie_enable_msi()
612 irq_set_chained_handler_and_data(msi->irq_msi1, in nwl_pcie_enable_msi()
616 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in nwl_pcie_enable_msi()
617 if (msi->irq_msi0 < 0) in nwl_pcie_enable_msi()
618 return -EINVAL; in nwl_pcie_enable_msi()
620 irq_set_chained_handler_and_data(msi->irq_msi0, in nwl_pcie_enable_msi()
627 return -EIO; in nwl_pcie_enable_msi()
639 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
670 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
682 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
684 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
703 if (of_dma_is_coherent(dev->of_node)) in nwl_pcie_bridge_init()
713 dev_err(dev, "ECAM is not present\n"); in nwl_pcie_bridge_init()
717 /* Enable ECAM */ in nwl_pcie_bridge_init()
726 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
728 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
737 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
738 if (pcie->irq_misc < 0) in nwl_pcie_bridge_init()
739 return -EINVAL; in nwl_pcie_bridge_init()
741 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
746 pcie->irq_misc); in nwl_pcie_bridge_init()
780 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
785 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
786 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
787 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
788 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
791 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
792 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
793 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
794 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
797 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
798 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
799 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
800 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
803 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
804 if (pcie->irq_intx < 0) in nwl_pcie_parse_dt()
805 return pcie->irq_intx; in nwl_pcie_parse_dt()
807 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
811 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { in nwl_pcie_parse_dt()
812 pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); in nwl_pcie_parse_dt()
813 if (PTR_ERR(pcie->phy[i]) == -ENODEV) { in nwl_pcie_parse_dt()
814 pcie->phy[i] = NULL; in nwl_pcie_parse_dt()
818 if (IS_ERR(pcie->phy[i])) in nwl_pcie_parse_dt()
819 return PTR_ERR(pcie->phy[i]); in nwl_pcie_parse_dt()
826 { .compatible = "xlnx,nwl-pcie-2.11", },
832 struct device *dev = &pdev->dev; in nwl_pcie_probe()
839 return -ENODEV; in nwl_pcie_probe()
844 pcie->dev = dev; in nwl_pcie_probe()
852 pcie->clk = devm_clk_get(dev, NULL); in nwl_pcie_probe()
853 if (IS_ERR(pcie->clk)) in nwl_pcie_probe()
854 return PTR_ERR(pcie->clk); in nwl_pcie_probe()
856 err = clk_prepare_enable(pcie->clk); in nwl_pcie_probe()
880 bridge->sysdata = pcie; in nwl_pcie_probe()
881 bridge->ops = &nwl_pcie_ops; in nwl_pcie_probe()
898 clk_disable_unprepare(pcie->clk); in nwl_pcie_probe()
907 clk_disable_unprepare(pcie->clk); in nwl_pcie_remove()
912 .name = "nwl-pcie",