| /freebsd/share/misc/ |
| H A D | pci_vendors | 5 # Date: 2024-09-20 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
49 7a19 PCI-to-PCI Bridge
53 7a29 PCI-to-PCI Bridge
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| /freebsd/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5
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| H A D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remotepro
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| H A D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fs
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| /freebsd/share/man/man4/ |
| H A D | uath.4 | 27 .Bd -ragged -offset indent
39 .Bd -literal -offset indent
48 The AR5005UG chipset is made of an AR5523 multiprotocol MAC/baseband processor
49 and an AR2112 Radio-on-a-Chip that can operate between 2300 and 2500 MHz
52 The AR5005UX chipset is made of an AR5523 multiprotocol MAC/baseband processor
53 and an AR5112 dual band Radio-on-a-Chip that can operate between 2300 and
56 The AR5005UG and AR5005UX chipsets both have an integrated 32-bit MIPS
57 R4000-class processor that runs a firmware and manages, among other things,
84 .Bl -column "TRENDware International TEW-444UB" "AR5005UX"
89 .\".It Li "D-Link DWL-AG132" Ta AR5005UX
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| H A D | run.4 | 1 .\"-
2 .\" SPDX-License-Identifier: ISC
30 .Bd -ragged -offset indent
41 .Bd -ragged -offset indent
48 .Bd -literal -offset indent
59 an RT2720 (1T2R) or RT2750 (dual-band 1T2R) radio transceiver.
62 an RT2820 (2T3R) or RT2850 (dual-band 2T3R) radio transceiver.
64 The RT3000U is a single-chip solution based on an RT3070 MAC/BBP and
65 an RT3020 (1T1R), RT3021 (1T2R) or RT3022 (2T2R) single-band radio
68 The RT3900E is a single-chip USB 2.0 802.11n solution.
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | nvidia,tegra210-mbdrc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-mbdrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 single full band or a dual band or a multi band dynamic processor.
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Mohan Kumar <mkumard@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
23 - const: nvidia,tegra210-mbdrc
24 - items:
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| /freebsd/sys/contrib/device-tree/Bindings/arm/freescale/ |
| H A D | fsl,vf610-mscm-ir.txt | 1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
6 it controls the directed processor interrupts. The module is available in all
7 Vybrid SoC's but is only really useful in dual core configurations (VF6xx
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
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| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | cpm.txt | 1 * Freescale Communications Processor Module
10 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11 - reg : A 48-byte region beginning with CPCR.
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
24 - fsl,cpm-command : This value is ORed with the opcode and command flag
27 - fsl,cpm-brg : Indicates which baud rate generator the device
32 - reg : Unless otherwise specified, the first resource represents the
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| /freebsd/sys/contrib/device-tree/Bindings/ |
| H A D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-ma
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| H A D | numa.txt | 6 1 - Introduction
12 Processor accesses to memory within the local NUMA node is generally faster
13 than processor accesses to memory outside of the local NUMA node.
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
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| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx6_audmux.c | 1 /*-
29 * Chapter 16, i.MX 6Dual/6Quad Applications Processor Reference Manual,
53 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
55 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
57 #define AUDMUX_PTCR(n) (0x8 * (n - 1)) /* Port Timing Control Register */
66 #define AUDMUX_PDCR(n) (0x8 * (n - 1) + 0x4) /* Port Data Control Reg */
69 #define PDCR_RXDSEL_PORT(n) (n - 1)
80 { -1, 0 }
90 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-audmux")) in audmux_probe()
121 if (bus_alloc_resources(dev, audmux_spec, sc->res)) { in audmux_attach()
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| /freebsd/crypto/openssl/crypto/sha/asm/ |
| H A D | sha1-s390x.pl | 2 # Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
12 # project. The module is, however, dual licensed under OpenSSL and
28 # instructions to favour dual-issue z10 pipeline. On z10 hardware is
33 # Adapt for -m31 build. If kernel supports what's called "highgprs"
34 # feature on Linux [see /proc/cpuinfo], it's possible to use 64-bit
35 # instructions and achieve "64-bit" performance even in 31-bit legacy
37 # processor, as long as it's "z-CPU". Latter implies that the code
81 lg $prefetch,$stdframe($sp) ### Xupdate(16) warm-up
172 .size Ktable,.-Ktable
187 brc 1,.-4 # pay attention to "partial completion"
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| H A D | sha512-s390x.pl | 2 # Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
12 # project. The module is, however, dual licensed under OpenSSL and
33 # favour dual-issue z10 pipeline. Hardware SHA256/512 is ~4.7x faster
38 # Adapt for -m31 build. If kernel supports what's called "highgprs"
39 # feature on Linux [see /proc/cpuinfo], it's possible to use 64-bit
40 # instructions and achieve "64-bit" performance even in 31-bit legacy
42 # processor, as long as it's "z-CPU". Latter implies that the code
44 # perform 2.4x and SHA512 - 13x better than code generated by gcc 4.3.
124 $ROT $t1,$t1,`$Sigma1[2]-$Sigma1[1]`
141 $ROT $t0,$t0,`$Sigma0[2]-$Sigma0[1]`
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM4.td | 1 //==- ARMScheduleM4.td - Cortex-M4 Scheduling Definitions -*- tablegen -*-====//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the SchedRead/Write data for the ARM Cortex-M4 processor.
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 1; // Only IT can be dual-issued, so assume single-issue
15 let MicroOpBufferSize = 0; // In-order
16 let LoadLatency = 2; // Latency when not pipelined, not pc-relative
28 // Cortex-M4 is in-order.
105 // Most FP instructions are single-cycle latency, except MAC's, Div's and Sqrt's.
|
| H A D | ARMScheduleR52.td | 1 //==- ARMScheduleR52.td - Cortex-R52 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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| H A D | ARMScheduleM7.td | 1 //=- ARMScheduleM7.td - ARM Cortex-M7 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 2; // Dual issue for most instructions.
15 let MicroOpBufferSize = 0; // The Cortex-M7 is in-order.
16 let LoadLatency = 2; // Best case for load-use case.
24 //===--------------------------------------------------------------------===//
25 // The Cortex-M7 has two ALU, two LOAD, a STORE, a MAC, a BRANCH and a VFP
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| H A D | ARMScheduleM55.td | 1 //==- ARMScheduleM55.td - Arm Cortex-M55 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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| /freebsd/sys/dev/isp/ |
| H A D | DriverManual.txt | 54 PCI and SBus SCSI cards, and now also drove the QLogic 2100 FC-AL HBA.
56 After this, ports to non-NetBSD platforms became interesting as well.
65 mode support has been added, and 2300 support as well as an FC-IP stack
71 Normally you design via top-down methodologies and set an initial goal
76 as I perceive them to be now- not necessarily what they started as.
83 dual channel PCI Ultra2 and PCI Ultra3 cards as well as the older PCI
90 as well as private loop and private loop, direct-attach topologies.
91 FC-IP support is also a goal.
119 The QLogic HBA cards all contain a tiny 16-bit RISC-like processor and
122 to a set of dual-ranked 16 bit incoming and outgoing mailbox registers
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| /freebsd/share/man/man5/ |
| H A D | make.conf.5 | 34 contains system-wide settings that will apply to every build using
71 if the system-wide settings are not suitable for a particular build.
130 .Bl -tag -width Ar
133 Instructs the top-level makefile in the source tree (normally
137 is up-to-date.
151 Controls which processor should be targeted for generated
153 This controls processor-specific optimizations in
193 .Bd -literal -offset indent
194 INSTALL+= -C
234 .Bl -tag -width Ar
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| /freebsd/contrib/llvm-project/compiler-rt/lib/builtins/cpu_model/ |
| H A D | x86.c | 1 //===-- cpu_model/x86.c - Support for __cpu_model builtin --------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
19 #error This file is intended only for x86-based targets
145 // has some not one-to-one mapped in llvm.
264 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
302 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
361 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 in detectX86FamilyModel()
362 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 in detectX86FamilyModel()
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| /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
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| /freebsd/sys/dev/qat/qat_api/include/ |
| H A D | cpa.h | 5 * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
292 #define CPA_STATUS_FAIL (-1)
296 #define CPA_STATUS_RETRY (-2)
300 #define CPA_STATUS_RESOURCE (-3)
306 #define CPA_STATUS_INVALID_PARAM (-4)
310 #define CPA_STATUS_FATAL (-5)
315 #define CPA_STATUS_UNSUPPORTED (-6)
321 #define CPA_STATUS_RESTARTING (-7)
424 /**< Cryptography - Asymmetric service */
426 /**< Cryptography - Symmetric service */
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| /freebsd/sys/contrib/dev/acpica/include/ |
| H A D | actbl2.h | 3 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)
11 * Some or all of this work - Copyright (c) 1999 - 2023, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
191 #define ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */
195 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
204 * All tables must be byte-packed to match the ACPI specification, since
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| /freebsd/sys/arm/allwinner/ |
| H A D | aw_mp.c | 1 /*-
47 /* Register for all dual-core SoC */
49 /* Register for all quad-core SoC */
54 /* Register for multi-cluster SoC */
103 mp_maxid = ncpu - 1; in aw_mp_setmaxid()
136 * debug access to the processor. in aw_mp_start_ap()
166 /* Clear power-off gating */ in aw_mp_start_ap()
181 /* De-assert cpu core reset */ in aw_mp_start_ap()
211 /* Assert power-on reset */ in aw_mc_mp_start_cpu()
229 /* Clear power-off gating */ in aw_mc_mp_start_cpu()
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