1*c66ec88fSEmmanuel VadotFreescale Vybrid Miscellaneous System Control - Interrupt Router 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThe MSCM IP contains multiple sub modules, this binding describes the second 4*c66ec88fSEmmanuel Vadotblock of registers which control the interrupt router. The interrupt router 5*c66ec88fSEmmanuel Vadotallows to configure the recipient of each peripheral interrupt. Furthermore 6*c66ec88fSEmmanuel Vadotit controls the directed processor interrupts. The module is available in all 7*c66ec88fSEmmanuel VadotVybrid SoC's but is only really useful in dual core configurations (VF6xx 8*c66ec88fSEmmanuel Vadotwhich comes with a Cortex-A5/Cortex-M4 combination). 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel VadotRequired properties: 11*c66ec88fSEmmanuel Vadot- compatible: "fsl,vf610-mscm-ir" 12*c66ec88fSEmmanuel Vadot- reg: the register range of the MSCM Interrupt Router 13*c66ec88fSEmmanuel Vadot- fsl,cpucfg: The handle to the MSCM CPU configuration node, required 14*c66ec88fSEmmanuel Vadot to get the current CPU ID 15*c66ec88fSEmmanuel Vadot- interrupt-controller: Identifies the node as an interrupt controller 16*c66ec88fSEmmanuel Vadot- #interrupt-cells: Two cells, interrupt number and cells. 17*c66ec88fSEmmanuel Vadot The hardware interrupt number according to interrupt 18*c66ec88fSEmmanuel Vadot assignment of the interrupt router is required. 19*c66ec88fSEmmanuel Vadot Flags get passed only when using GIC as parent. Flags 20*c66ec88fSEmmanuel Vadot encoding as documented by the GIC bindings. 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel VadotExample: 23*c66ec88fSEmmanuel Vadot mscm_ir: interrupt-controller@40001800 { 24*c66ec88fSEmmanuel Vadot compatible = "fsl,vf610-mscm-ir"; 25*c66ec88fSEmmanuel Vadot reg = <0x40001800 0x400>; 26*c66ec88fSEmmanuel Vadot fsl,cpucfg = <&mscm_cpucfg>; 27*c66ec88fSEmmanuel Vadot interrupt-controller; 28*c66ec88fSEmmanuel Vadot #interrupt-cells = <2>; 29*c66ec88fSEmmanuel Vadot interrupt-parent = <&intc>; 30*c66ec88fSEmmanuel Vadot } 31