1f0583578SRuslan Bukin /*-
2f0583578SRuslan Bukin * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3f0583578SRuslan Bukin * All rights reserved.
4f0583578SRuslan Bukin *
5f0583578SRuslan Bukin * Redistribution and use in source and binary forms, with or without
6f0583578SRuslan Bukin * modification, are permitted provided that the following conditions
7f0583578SRuslan Bukin * are met:
8f0583578SRuslan Bukin * 1. Redistributions of source code must retain the above copyright
9f0583578SRuslan Bukin * notice, this list of conditions and the following disclaimer.
10f0583578SRuslan Bukin * 2. Redistributions in binary form must reproduce the above copyright
11f0583578SRuslan Bukin * notice, this list of conditions and the following disclaimer in the
12f0583578SRuslan Bukin * documentation and/or other materials provided with the distribution.
13f0583578SRuslan Bukin *
14f0583578SRuslan Bukin * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15f0583578SRuslan Bukin * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16f0583578SRuslan Bukin * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17f0583578SRuslan Bukin * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18f0583578SRuslan Bukin * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19f0583578SRuslan Bukin * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20f0583578SRuslan Bukin * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21f0583578SRuslan Bukin * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22f0583578SRuslan Bukin * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23f0583578SRuslan Bukin * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24f0583578SRuslan Bukin * SUCH DAMAGE.
25f0583578SRuslan Bukin */
26f0583578SRuslan Bukin
27f0583578SRuslan Bukin /*
28f0583578SRuslan Bukin * i.MX6 Digital Audio Multiplexer (AUDMUX)
29f0583578SRuslan Bukin * Chapter 16, i.MX 6Dual/6Quad Applications Processor Reference Manual,
30f0583578SRuslan Bukin * Rev. 1, 04/2013
31f0583578SRuslan Bukin */
32f0583578SRuslan Bukin
33f0583578SRuslan Bukin #include <sys/param.h>
34f0583578SRuslan Bukin #include <sys/systm.h>
35f0583578SRuslan Bukin #include <sys/bus.h>
36f0583578SRuslan Bukin #include <sys/kernel.h>
37f0583578SRuslan Bukin #include <sys/module.h>
38f0583578SRuslan Bukin #include <sys/malloc.h>
39f0583578SRuslan Bukin #include <sys/endian.h>
40f0583578SRuslan Bukin #include <sys/rman.h>
41f0583578SRuslan Bukin #include <sys/timeet.h>
42f0583578SRuslan Bukin #include <sys/timetc.h>
43f0583578SRuslan Bukin
44f0583578SRuslan Bukin #include <dev/ofw/openfirm.h>
45f0583578SRuslan Bukin #include <dev/ofw/ofw_bus.h>
46f0583578SRuslan Bukin #include <dev/ofw/ofw_bus_subr.h>
47f0583578SRuslan Bukin
48f0583578SRuslan Bukin #include <machine/bus.h>
49f0583578SRuslan Bukin #include <machine/cpu.h>
50f0583578SRuslan Bukin #include <machine/intr.h>
51f0583578SRuslan Bukin
52f0583578SRuslan Bukin #define READ4(_sc, _reg) \
53f0583578SRuslan Bukin bus_space_read_4(_sc->bst, _sc->bsh, _reg)
54f0583578SRuslan Bukin #define WRITE4(_sc, _reg, _val) \
55f0583578SRuslan Bukin bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
56f0583578SRuslan Bukin
57f0583578SRuslan Bukin #define AUDMUX_PTCR(n) (0x8 * (n - 1)) /* Port Timing Control Register */
58f0583578SRuslan Bukin #define PTCR_TFS_DIR (1 << 31) /* Transmit Frame Sync Direction Control */
59f0583578SRuslan Bukin #define PTCR_TFSEL_S 27 /* Transmit Frame Sync Select */
60f0583578SRuslan Bukin #define PTCR_TFSEL_M 0xf
61f0583578SRuslan Bukin #define PTCR_TCLKDIR (1 << 26) /* Transmit Clock Direction Control */
62f0583578SRuslan Bukin #define PTCR_TCSEL_S 22 /* Transmit Clock Select. */
63f0583578SRuslan Bukin #define PTCR_TCSEL_M 0xf
64f0583578SRuslan Bukin #define PTCR_RFS_DIR (1 << 21) /* Receive Frame Sync Direction Control */
65f0583578SRuslan Bukin #define PTCR_SYN (1 << 11)
66f0583578SRuslan Bukin #define AUDMUX_PDCR(n) (0x8 * (n - 1) + 0x4) /* Port Data Control Reg */
67f0583578SRuslan Bukin #define PDCR_RXDSEL_S 13 /* Receive Data Select */
68f0583578SRuslan Bukin #define PDCR_RXDSEL_M 0x3
69f0583578SRuslan Bukin #define PDCR_RXDSEL_PORT(n) (n - 1)
70f0583578SRuslan Bukin
71f0583578SRuslan Bukin struct audmux_softc {
72f0583578SRuslan Bukin struct resource *res[1];
73f0583578SRuslan Bukin bus_space_tag_t bst;
74f0583578SRuslan Bukin bus_space_handle_t bsh;
75f0583578SRuslan Bukin void *ih;
76f0583578SRuslan Bukin };
77f0583578SRuslan Bukin
78f0583578SRuslan Bukin static struct resource_spec audmux_spec[] = {
79f0583578SRuslan Bukin { SYS_RES_MEMORY, 0, RF_ACTIVE },
80f0583578SRuslan Bukin { -1, 0 }
81f0583578SRuslan Bukin };
82f0583578SRuslan Bukin
83f0583578SRuslan Bukin static int
audmux_probe(device_t dev)84f0583578SRuslan Bukin audmux_probe(device_t dev)
85f0583578SRuslan Bukin {
86f0583578SRuslan Bukin
87f0583578SRuslan Bukin if (!ofw_bus_status_okay(dev))
88f0583578SRuslan Bukin return (ENXIO);
89f0583578SRuslan Bukin
90f0583578SRuslan Bukin if (!ofw_bus_is_compatible(dev, "fsl,imx6q-audmux"))
91f0583578SRuslan Bukin return (ENXIO);
92f0583578SRuslan Bukin
93f0583578SRuslan Bukin device_set_desc(dev, "i.MX6 Digital Audio Multiplexer");
94f0583578SRuslan Bukin return (BUS_PROBE_DEFAULT);
95f0583578SRuslan Bukin }
96f0583578SRuslan Bukin
97f0583578SRuslan Bukin static int
audmux_configure(struct audmux_softc * sc,int ssi_port,int audmux_port)98f0583578SRuslan Bukin audmux_configure(struct audmux_softc *sc,
99f0583578SRuslan Bukin int ssi_port, int audmux_port)
100f0583578SRuslan Bukin {
101f0583578SRuslan Bukin uint32_t reg;
102f0583578SRuslan Bukin
103f0583578SRuslan Bukin /* Direction: output */
104f0583578SRuslan Bukin reg = (PTCR_TFS_DIR | PTCR_TCLKDIR | PTCR_SYN);
105f0583578SRuslan Bukin WRITE4(sc, AUDMUX_PTCR(audmux_port), reg);
106f0583578SRuslan Bukin
107f0583578SRuslan Bukin /* Select source */
108f0583578SRuslan Bukin reg = (PDCR_RXDSEL_PORT(ssi_port) << PDCR_RXDSEL_S);
109f0583578SRuslan Bukin WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);
110f0583578SRuslan Bukin
111f0583578SRuslan Bukin return (0);
112f0583578SRuslan Bukin }
113f0583578SRuslan Bukin
114f0583578SRuslan Bukin static int
audmux_attach(device_t dev)115f0583578SRuslan Bukin audmux_attach(device_t dev)
116f0583578SRuslan Bukin {
117f0583578SRuslan Bukin struct audmux_softc *sc;
118f0583578SRuslan Bukin
119f0583578SRuslan Bukin sc = device_get_softc(dev);
120f0583578SRuslan Bukin
121f0583578SRuslan Bukin if (bus_alloc_resources(dev, audmux_spec, sc->res)) {
122f0583578SRuslan Bukin device_printf(dev, "could not allocate resources\n");
123f0583578SRuslan Bukin return (ENXIO);
124f0583578SRuslan Bukin }
125f0583578SRuslan Bukin
126f0583578SRuslan Bukin /* Memory interface */
127f0583578SRuslan Bukin sc->bst = rman_get_bustag(sc->res[0]);
128f0583578SRuslan Bukin sc->bsh = rman_get_bushandle(sc->res[0]);
129f0583578SRuslan Bukin
130f0583578SRuslan Bukin /*
131f0583578SRuslan Bukin * Direct SSI1 output to AUDMUX5 pins.
132f0583578SRuslan Bukin * TODO: dehardcore this.
133f0583578SRuslan Bukin */
134f0583578SRuslan Bukin audmux_configure(sc, 1, 5);
135f0583578SRuslan Bukin
136f0583578SRuslan Bukin return (0);
137f0583578SRuslan Bukin };
138f0583578SRuslan Bukin
139f0583578SRuslan Bukin static device_method_t audmux_methods[] = {
140f0583578SRuslan Bukin /* Device interface */
141f0583578SRuslan Bukin DEVMETHOD(device_probe, audmux_probe),
142f0583578SRuslan Bukin DEVMETHOD(device_attach, audmux_attach),
143f0583578SRuslan Bukin { 0, 0 }
144f0583578SRuslan Bukin };
145f0583578SRuslan Bukin
146f0583578SRuslan Bukin static driver_t audmux_driver = {
147f0583578SRuslan Bukin "audmux",
148f0583578SRuslan Bukin audmux_methods,
149f0583578SRuslan Bukin sizeof(struct audmux_softc),
150f0583578SRuslan Bukin };
151f0583578SRuslan Bukin
152*ea538dabSJohn Baldwin DRIVER_MODULE(audmux, simplebus, audmux_driver, 0, 0);
153