Lines Matching +full:dual +full:- +full:processor

1 //==- ARMScheduleM55.td - Arm Cortex-M55 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the scheduling model for the Arm Cortex-M55 processors.
11 //===----------------------------------------------------------------------===//
13 // ===---------------------------------------------------------------------===//
14 // Cortex-M55 is a lot like the M4/M33 in terms of scheduling. It technically
17 // Cortex-M4 are MVE instructions and the ability to dual issue thumb1
24 // pipelines across 4 stages (E1-E4). These pipelines are "control",
33 // the execution of the first-beat-of-the-second-instruction can overlap with
34 // the second-beat-of-the-first. For example a sequence of VLDR;VADD;VMUL;VSTR
52 // Dual Issue
54 // Cortex-M55 can dual issue two 16-bit T1 instructions providing one is one of
61 // Thumb2SizeReductionPass has not been run yet. Especially pre-ra scheduling
69 //  All instructions we cannot dual issue are "SingleIssue=1" (MVE/FP and T2
72 //    These become the primary instruction in a dual issue pair (the normal
80 // Post-RA scheduling sees what is T1/T2. It may also be possible to write a
85   let MicroOpBufferSize = 0;      // Explicitly set to zero since M55 is in-order.
86   let IssueWidth = 2;             // There is some dual-issue support in M55.
101 //===----------------------------------------------------------------------===//
102 // Define each kind of processor resource and number available.
105 // M55 is in-order.
118 //===----------------------------------------------------------------------===//
119 // Subtarget-specific SchedWrite types which both map the ProcResources and
126 // Generic writes for Flags, GRPs and other extra operands (eg post-inc, vadc flags, vaddlv etc)
132 // instructions that may be shrank to T1 (and can be dual issued) are
153 // be dual issued with one of the above. This list is optimistic.
175 // CX instructions take 2 (or more) cycles. Again T1 instructions may be dual
219 // Dual Issue instructions
227 // Thumb 2 instructions that could be reduced to a dual issuable Thumb 1
308 def M55GatherQRead : SchedReadAdvance<-4>;
323 def : InstRW<[M55Write2LSE2], (instregex "MVE_VLD[24][0-3]_(8|16|32)$")>;
325 def : InstRW<[M55Write2LSE2, M55WriteLat1], (instregex "MVE_VLD[24][0-3]_(8|16|32)_wb$")>;
458 def : InstRW<[M55WriteFloatE3], (instregex "VINSH$", "VMOVH$", "VMOVHR$", "VMOVSR$", "VMOVDRR$")>; // VINS, VMOVX, to-FP reg movs