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/linux/drivers/net/wireless/intel/iwlwifi/pcie/
H A D	ctxt-info.c	50 struct iwl_dram_data dram) in iwl_pcie_ctxt_info_alloc_dma() argument 52 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, in iwl_pcie_ctxt_info_alloc_dma() 53 &dram->physical); in iwl_pcie_ctxt_info_alloc_dma() 54 if (!dram->block) in iwl_pcie_ctxt_info_alloc_dma() 57 dram->size = len; in iwl_pcie_ctxt_info_alloc_dma() 58 memcpy(dram->block, data, len); in iwl_pcie_ctxt_info_alloc_dma() 65 struct iwl_self_init_dram dram = &trans->init_dram; in iwl_pcie_ctxt_info_free_paging() local 68 if (!dram->paging) { in iwl_pcie_ctxt_info_free_paging() 69 WARN_ON(dram->paging_cnt); in iwl_pcie_ctxt_info_free_paging() 74 for (i = 0; i < dram->paging_cnt; i++) in iwl_pcie_ctxt_info_free_paging() [all …]
H A D	iwl-context-info.h	9 /* maximum number of DRAM map entries supported by FW / 81 struct iwl_context_info_dram_nonfseq - images DRAM map 82 * each entry in the map represents a DRAM chunk of up to 32 KB 83 * @umac_img: UMAC image DRAM map 84 * @lmac_img: LMAC image DRAM map 85 * @virtual_img: paged image DRAM map 119 * @core_dump_addr: core dump (debug DRAM address) start address 143 * dumping DRAM addresses 166 * @dram: firmware image addresses in DRAM 180 struct iwl_context_info_dram_nonfseq dram; member [all …]
H A D	ctxt-info-v2.c	50 "WRT: Applying DRAM buffer destination\n"); in iwl_pcie_ctxt_info_dbg_enable() 83 "WRT: Applying DRAM destination (debug_token_config=%u)\n", in iwl_pcie_ctxt_info_dbg_enable() 86 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", in iwl_pcie_ctxt_info_dbg_enable() 192 /* allocate ucode sections in dram and set addresses / in iwl_pcie_ctxt_info_v2_alloc() 193 ret = iwl_pcie_init_fw_sec(trans, img, &prph_scratch->dram.common); in iwl_pcie_ctxt_info_v2_alloc() 235 BUILD_BUG_ON(offsetofend(typeof(prph_scratch), dram.common) + in iwl_pcie_ctxt_info_v2_alloc() 236 sizeof(prph_scratch->dram.fseq_img) != in iwl_pcie_ctxt_info_v2_alloc() 244 dram.common)); in iwl_pcie_ctxt_info_v2_alloc() 355 struct iwl_dram_data *dram) in iwl_pcie_load_payloads_contig() argument 373 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, in iwl_pcie_load_payloads_contig() [all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	memory.json	125 …on": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.", 128 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", 135 …on": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.", 138 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", 145 …Description": "Counts all prefetch code reads that miss the LLC and the data returned from dram.", 148 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM", 155 …Description": "Counts all prefetch data reads that miss the LLC and the data returned from dram.", 158 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM", 165 …"BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.", 168 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM", [all …]
/linux/drivers/ras/amd/atl/
H A D	reg_fields.h	`71 * D18F0x114 [DRAM Limit Address] 76 * D18F7xE08 [DRAM Address Control] 79 * D18F7x208 [DRAM Address Control] 132 * DRAM Address Range Valid 139 * D18F0x110 [DRAM Base Address] 144 * D18F7xE08 [DRAM Address Control] 147 * D18F7x208 [DRAM Address Control] 153 * DRAM Base Address 160 * D18F0x110 [DRAM Base Address] 165 * D18F7xE00 [DRAM Base Address] [all …]`
/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A D	memory.json	11 "BriefDescription": "Offcore data reads satisfied by any DRAM", 31 "BriefDescription": "Offcore data reads satisfied by the local DRAM", 41 "BriefDescription": "Offcore data reads satisfied by a remote DRAM", 51 "BriefDescription": "Offcore code reads satisfied by any DRAM", 71 "BriefDescription": "Offcore code reads satisfied by the local DRAM", 81 "BriefDescription": "Offcore code reads satisfied by a remote DRAM", 91 "BriefDescription": "Offcore requests satisfied by any DRAM", 111 "BriefDescription": "Offcore requests satisfied by the local DRAM", 121 "BriefDescription": "Offcore requests satisfied by a remote DRAM", 131 "BriefDescription": "Offcore RFO requests satisfied by any DRAM", [all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A D	memory.json	3 "BriefDescription": "Offcore data reads satisfied by any DRAM", 23 "BriefDescription": "Offcore data reads satisfied by the local DRAM", 33 "BriefDescription": "Offcore data reads satisfied by a remote DRAM", 43 "BriefDescription": "Offcore code reads satisfied by any DRAM", 63 "BriefDescription": "Offcore code reads satisfied by the local DRAM", 73 "BriefDescription": "Offcore code reads satisfied by a remote DRAM", 83 "BriefDescription": "Offcore requests satisfied by any DRAM", 103 "BriefDescription": "Offcore requests satisfied by the local DRAM", 113 "BriefDescription": "Offcore requests satisfied by a remote DRAM", 123 "BriefDescription": "Offcore RFO requests satisfied by any DRAM", [all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A D	memory.json	3 "BriefDescription": "Offcore data reads satisfied by any DRAM", 23 "BriefDescription": "Offcore data reads satisfied by the local DRAM", 33 "BriefDescription": "Offcore data reads satisfied by a remote DRAM", 43 "BriefDescription": "Offcore code reads satisfied by any DRAM", 63 "BriefDescription": "Offcore code reads satisfied by the local DRAM", 73 "BriefDescription": "Offcore code reads satisfied by a remote DRAM", 83 "BriefDescription": "Offcore requests satisfied by any DRAM", 103 "BriefDescription": "Offcore requests satisfied by the local DRAM", 113 "BriefDescription": "Offcore requests satisfied by a remote DRAM", 123 "BriefDescription": "Offcore RFO requests satisfied by any DRAM", [all …]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	uncore-memory.json	3 …ion": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channel… 8 …ion": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channel… 18 …s may merge to a single write command to DRAM. Therefore, the total request count may be higher th… 23 …on": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channel… 28 …on": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channel… 33 …ion": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channel… 38 …ion": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channel… 48 …s may merge to a single write command to DRAM. Therefore, the total request count may be higher th… 53 …on": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channel… 58 …on": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channel… [all …]
/linux/tools/perf/pmu-events/arch/x86/westmereep-sp/
H A D	memory.json	3 "BriefDescription": "Offcore data reads satisfied by any DRAM", 23 "BriefDescription": "Offcore data reads satisfied by the local DRAM", 33 "BriefDescription": "Offcore data reads satisfied by a remote DRAM", 43 "BriefDescription": "Offcore code reads satisfied by any DRAM", 63 "BriefDescription": "Offcore code reads satisfied by the local DRAM", 73 "BriefDescription": "Offcore code reads satisfied by a remote DRAM", 83 "BriefDescription": "Offcore requests satisfied by any DRAM", 103 "BriefDescription": "Offcore requests satisfied by the local DRAM", 113 "BriefDescription": "Offcore requests satisfied by a remote DRAM", 123 "BriefDescription": "Offcore RFO requests satisfied by any DRAM", [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	data-fabric.json	36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	data-fabric.json	36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	data-fabric.json	36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe… 92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
/linux/Documentation/devicetree/bindings/memory-controllers/
H A D	rockchip,rk3399-dmc.yaml	71 SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock). 100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated 130 When the DRAM type is DDR3, this parameter defines the ODT disable 132 the ODT on the DRAM side and controller side are both disabled. 138 When the DRAM type is DDR3, this parameter defines the DRAM side drive 146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT 154 When the DRAM type is DDR3, this parameter defines the phy side CA line 162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line 170 When the DRAM type is DDR3, this parameter defines the PHY side ODT 178 When the DRAM type is LPDDR3, this parameter defines then ODT disable [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	uncore-memory.json	8 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu… 19 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p… 25 "BriefDescription": "DRAM Activate Count : All Activates", 30 …DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this cha… 35 "BriefDescription": "DRAM Activate Count : Activate due to Bypass", 41 …DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on… 46 "BriefDescription": "All DRAM CAS commands issued", 51 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.", 56 "BriefDescription": "All DRAM read CAS commands issued (including underfills)", 61 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu… [all …]
H A D	memory.json	31 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 34 "EventName": "OCR.ALL_CODE_RD.DRAM", 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 64 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 70 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 97 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 100 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 103 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST co… 130 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 136 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST co… [all …]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	uncore-memory.json	3 …issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data… 12 …DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. … 21 …issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data… 30 …issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data… 39 …DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. … 48 …issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data…
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	memory.json	180 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 183 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 186 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST co… 202 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 208 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 213 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory… 219 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory… 224 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 227 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 230 …"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counter… [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	memory.json	180 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 183 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 186 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST co… 202 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 208 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 213 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory… 219 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory… 224 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 227 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 230 …"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counter… [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	memory.json	202 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 205 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 208 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST co… 224 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 230 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 235 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 238 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 241 …"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counter… 257 …ds that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 263 …ds that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	memory.json	31 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 34 "EventName": "OCR.ALL_CODE_RD.DRAM", 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 64 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 70 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 97 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 100 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 103 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST co… 130 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 136 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST co… [all …]
/linux/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/
H A D	ali_drw.json	38 "BriefDescription": "A write data cycle at DFI interface (to DRAM).", 45 "BriefDescription": "A read data cycle at DFI interface (to DRAM).", 73 "BriefDescription": "An Activate(ACT) command to DRAM.", 80 "BriefDescription": "A Read or Write CAS command to DRAM.", 87 "BriefDescription": "An Activate(ACT) command for read to DRAM.", 94 "BriefDescription": "A Read CAS command to DRAM.", 101 "BriefDescription": "A Write CAS command to DRAM.", 108 "BriefDescription": "A Masked Write command to DRAM.", 115 "BriefDescription": "A Precharge(PRE) command to DRAM.", 255 "BriefDescription": "An auto-refresh(REF) command to DRAM.", [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A D	uncore-memory.json	3 …ion": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channel… 8 …tion": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channel… 13 …DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. … 22 …"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum o… 27 …"PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all c… 32 …DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. … 41 "BriefDescription": "ACT command for a read request sent to DRAM", 49 "BriefDescription": "ACT command sent to DRAM", 57 "BriefDescription": "ACT command for a write request sent to DRAM", 65 "BriefDescription": "Read CAS command sent to DRAM", [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	uncore-memory.json	3 …ion": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channel… 8 …tion": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channel… 13 …DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. … 22 …"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum o… 27 …"PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all c… 32 …DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. … 41 "BriefDescription": "ACT command for a read request sent to DRAM", 49 "BriefDescription": "ACT command sent to DRAM", 57 "BriefDescription": "ACT command for a write request sent to DRAM", 65 "BriefDescription": "Read CAS command sent to DRAM", [all …]
/linux/drivers/edac/
H A D	i3000_edac.c	25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller / 31 #define I3000_EDEAP 0x70 / Extended DRAM Error Address Pointer (8b) 36 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b) 68 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b) 70 * 7:0 DRAM ECC Syndrome 79 * 9 LOCK to non-DRAM Memory Flag (LCKF) 82 * 1 Multi-bit DRAM ECC Error Flag (DMERR) 83 * 0 Single-bit DRAM ECC Error Flag (DSERR) 95 * 9 SERR on LOCK to non-DRAM Memory 97 * 8 SERR on DRAM Refresh Timeout [all …]

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