1[ 2 { 3 "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", 4 "Counter": "1", 5 "EventCode": "0xff", 6 "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", 7 "PerPkg": "1", 8 "UMask": "0x20", 9 "Unit": "imc_free_running_0" 10 }, 11 { 12 "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 13 "Counter": "0", 14 "EventCode": "0xff", 15 "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", 16 "PerPkg": "1", 17 "UMask": "0x10", 18 "Unit": "imc_free_running_0" 19 }, 20 { 21 "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", 22 "Counter": "2", 23 "EventCode": "0xff", 24 "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", 25 "PerPkg": "1", 26 "UMask": "0x30", 27 "Unit": "imc_free_running_0" 28 }, 29 { 30 "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", 31 "Counter": "4", 32 "EventCode": "0xff", 33 "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", 34 "PerPkg": "1", 35 "UMask": "0x20", 36 "Unit": "imc_free_running_1" 37 }, 38 { 39 "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 40 "Counter": "3", 41 "EventCode": "0xff", 42 "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", 43 "PerPkg": "1", 44 "UMask": "0x10", 45 "Unit": "imc_free_running_1" 46 }, 47 { 48 "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", 49 "Counter": "5", 50 "EventCode": "0xff", 51 "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", 52 "PerPkg": "1", 53 "UMask": "0x30", 54 "Unit": "imc_free_running_1" 55 } 56] 57