1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2025 Intel Corporation 4 */ 5 #include <linux/dmi.h> 6 #include "iwl-trans.h" 7 #include "iwl-fh.h" 8 #include "iwl-context-info-v2.h" 9 #include "internal.h" 10 #include "iwl-prph.h" 11 12 static const struct dmi_system_id dmi_force_scu_active_approved_list[] = { 13 { .ident = "DELL", 14 .matches = { 15 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 16 }, 17 }, 18 { .ident = "DELL", 19 .matches = { 20 DMI_MATCH(DMI_SYS_VENDOR, "Alienware"), 21 }, 22 }, 23 /* keep last */ 24 {} 25 }; 26 27 static bool iwl_is_force_scu_active_approved(void) 28 { 29 return !!dmi_check_system(dmi_force_scu_active_approved_list); 30 } 31 32 static void 33 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 34 struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 35 u32 *control_flags) 36 { 37 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 38 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 39 u32 dbg_flags = 0; 40 41 if (!iwl_trans_dbg_ini_valid(trans)) { 42 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 43 44 iwl_pcie_alloc_fw_monitor(trans, 0); 45 46 if (fw_mon->size) { 47 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 48 49 IWL_DEBUG_FW(trans, 50 "WRT: Applying DRAM buffer destination\n"); 51 52 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 53 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 54 } 55 56 goto out; 57 } 58 59 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 60 61 switch (le32_to_cpu(fw_mon_cfg->buf_location)) { 62 case IWL_FW_INI_LOCATION_SRAM_PATH: 63 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 64 IWL_DEBUG_FW(trans, 65 "WRT: Applying SMEM buffer destination\n"); 66 break; 67 68 case IWL_FW_INI_LOCATION_NPK_PATH: 69 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; 70 IWL_DEBUG_FW(trans, 71 "WRT: Applying NPK buffer destination\n"); 72 break; 73 74 case IWL_FW_INI_LOCATION_DRAM_PATH: 75 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { 76 struct iwl_dram_data *frag = 77 &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 78 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 79 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 80 dbg_cfg->hwm_size = cpu_to_le32(frag->size); 81 dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset); 82 IWL_DEBUG_FW(trans, 83 "WRT: Applying DRAM destination (debug_token_config=%u)\n", 84 dbg_cfg->debug_token_config); 85 IWL_DEBUG_FW(trans, 86 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", 87 alloc_id, 88 trans->dbg.fw_mon_ini[alloc_id].num_frags); 89 } 90 break; 91 default: 92 IWL_DEBUG_FW(trans, "WRT: Invalid buffer destination (%d)\n", 93 le32_to_cpu(fw_mon_cfg->buf_location)); 94 } 95 out: 96 if (dbg_flags) 97 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 98 } 99 100 int iwl_pcie_ctxt_info_v2_alloc(struct iwl_trans *trans, 101 const struct iwl_fw *fw, 102 const struct fw_img *img) 103 { 104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 105 struct iwl_context_info_v2 *ctxt_info_v2; 106 struct iwl_prph_scratch *prph_scratch; 107 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 108 struct iwl_prph_info *prph_info; 109 u32 control_flags = 0; 110 u32 control_flags_ext = 0; 111 int ret; 112 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 113 trans->mac_cfg->base->min_txq_size); 114 115 switch (trans->conf.rx_buf_size) { 116 case IWL_AMSDU_DEF: 117 return -EINVAL; 118 case IWL_AMSDU_2K: 119 break; 120 case IWL_AMSDU_4K: 121 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 122 break; 123 case IWL_AMSDU_8K: 124 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 125 /* if firmware supports the ext size, tell it */ 126 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; 127 break; 128 case IWL_AMSDU_12K: 129 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 130 /* if firmware supports the ext size, tell it */ 131 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K; 132 break; 133 } 134 135 if (trans->conf.dsbr_urm_fw_dependent) 136 control_flags_ext |= IWL_PRPH_SCRATCH_EXT_URM_FW; 137 138 if (trans->conf.dsbr_urm_permanent) 139 control_flags_ext |= IWL_PRPH_SCRATCH_EXT_URM_PERM; 140 141 if (trans->conf.ext_32khz_clock_valid) 142 control_flags_ext |= IWL_PRPH_SCRATCH_EXT_32KHZ_CLK_VALID; 143 144 /* Allocate prph scratch */ 145 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 146 &trans_pcie->prph_scratch_dma_addr, 147 GFP_KERNEL); 148 if (!prph_scratch) 149 return -ENOMEM; 150 151 prph_sc_ctrl = &prph_scratch->ctrl_cfg; 152 153 prph_sc_ctrl->version.version = 0; 154 prph_sc_ctrl->version.mac_id = 155 cpu_to_le16((u16)trans->info.hw_rev); 156 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 157 158 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; 159 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; 160 161 if (trans->mac_cfg->imr_enabled) 162 control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN; 163 164 if (CSR_HW_REV_TYPE(trans->info.hw_rev) == IWL_CFG_MAC_TYPE_GL && 165 iwl_is_force_scu_active_approved()) { 166 control_flags |= IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE; 167 IWL_DEBUG_FW(trans, 168 "Context Info: Set SCU_FORCE_ACTIVE (0x%x) in control_flags\n", 169 IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE); 170 } 171 172 if (trans->do_top_reset) { 173 WARN_ON(trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_SC); 174 control_flags |= IWL_PRPH_SCRATCH_TOP_RESET; 175 } 176 177 /* initialize RX default queue */ 178 prph_sc_ctrl->rbd_cfg.free_rbd_addr = 179 cpu_to_le64(trans_pcie->rxq->bd_dma); 180 181 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 182 &control_flags); 183 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 184 prph_sc_ctrl->control.control_flags_ext = cpu_to_le32(control_flags_ext); 185 186 /* initialize the Step equalizer data */ 187 prph_sc_ctrl->step_cfg.mbx_addr_0 = 188 cpu_to_le32(trans->conf.mbx_addr_0_step); 189 prph_sc_ctrl->step_cfg.mbx_addr_1 = 190 cpu_to_le32(trans->conf.mbx_addr_1_step); 191 192 /* allocate ucode sections in dram and set addresses */ 193 ret = iwl_pcie_init_fw_sec(trans, img, &prph_scratch->dram.common); 194 if (ret) 195 goto err_free_prph_scratch; 196 197 /* Allocate prph information 198 * currently we don't assign to the prph info anything, but it would get 199 * assigned later 200 * 201 * We also use the second half of this page to give the device some 202 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't 203 * use this, but the hardware still reads/writes there and we can't let 204 * it go do that with a NULL pointer. 205 */ 206 BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2); 207 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE, 208 &trans_pcie->prph_info_dma_addr, 209 GFP_KERNEL); 210 if (!prph_info) { 211 ret = -ENOMEM; 212 goto err_free_prph_scratch; 213 } 214 215 /* Allocate context info */ 216 ctxt_info_v2 = dma_alloc_coherent(trans->dev, 217 sizeof(*ctxt_info_v2), 218 &trans_pcie->ctxt_info_dma_addr, 219 GFP_KERNEL); 220 if (!ctxt_info_v2) { 221 ret = -ENOMEM; 222 goto err_free_prph_info; 223 } 224 225 ctxt_info_v2->prph_info_base_addr = 226 cpu_to_le64(trans_pcie->prph_info_dma_addr); 227 ctxt_info_v2->prph_scratch_base_addr = 228 cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 229 230 /* 231 * This code assumes the FSEQ is last and we can make that 232 * optional; old devices _should_ be fine with a bigger size, 233 * but in simulation we check the size more precisely. 234 */ 235 BUILD_BUG_ON(offsetofend(typeof(*prph_scratch), dram.common) + 236 sizeof(prph_scratch->dram.fseq_img) != 237 sizeof(*prph_scratch)); 238 if (control_flags_ext & IWL_PRPH_SCRATCH_EXT_EXT_FSEQ) 239 ctxt_info_v2->prph_scratch_size = 240 cpu_to_le32(sizeof(*prph_scratch)); 241 else 242 ctxt_info_v2->prph_scratch_size = 243 cpu_to_le32(offsetofend(typeof(*prph_scratch), 244 dram.common)); 245 246 ctxt_info_v2->cr_head_idx_arr_base_addr = 247 cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 248 ctxt_info_v2->tr_tail_idx_arr_base_addr = 249 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2); 250 ctxt_info_v2->cr_tail_idx_arr_base_addr = 251 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4); 252 ctxt_info_v2->mtr_base_addr = 253 cpu_to_le64(trans_pcie->txqs.txq[trans->conf.cmd_queue]->dma_addr); 254 ctxt_info_v2->mcr_base_addr = 255 cpu_to_le64(trans_pcie->rxq->used_bd_dma); 256 ctxt_info_v2->mtr_size = 257 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 258 ctxt_info_v2->mcr_size = 259 cpu_to_le16(RX_QUEUE_CB_SIZE(iwl_trans_get_num_rbds(trans))); 260 261 trans_pcie->ctxt_info_v2 = ctxt_info_v2; 262 trans_pcie->prph_info = prph_info; 263 trans_pcie->prph_scratch = prph_scratch; 264 265 /* Allocate IML */ 266 trans_pcie->iml_len = fw->iml_len; 267 trans_pcie->iml = dma_alloc_coherent(trans->dev, fw->iml_len, 268 &trans_pcie->iml_dma_addr, 269 GFP_KERNEL); 270 if (!trans_pcie->iml) { 271 ret = -ENOMEM; 272 goto err_free_ctxt_info; 273 } 274 275 memcpy(trans_pcie->iml, fw->iml, fw->iml_len); 276 277 return 0; 278 279 err_free_ctxt_info: 280 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_v2), 281 trans_pcie->ctxt_info_v2, 282 trans_pcie->ctxt_info_dma_addr); 283 trans_pcie->ctxt_info_v2 = NULL; 284 err_free_prph_info: 285 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info, 286 trans_pcie->prph_info_dma_addr); 287 288 err_free_prph_scratch: 289 dma_free_coherent(trans->dev, 290 sizeof(*prph_scratch), 291 prph_scratch, 292 trans_pcie->prph_scratch_dma_addr); 293 return ret; 294 295 } 296 297 void iwl_pcie_ctxt_info_v2_kick(struct iwl_trans *trans) 298 { 299 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 300 301 iwl_enable_fw_load_int_ctx_info(trans, trans->do_top_reset); 302 303 /* kick FW self load */ 304 iwl_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie->ctxt_info_dma_addr); 305 iwl_write64(trans, CSR_IML_DATA_ADDR, trans_pcie->iml_dma_addr); 306 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie->iml_len); 307 308 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 309 CSR_AUTO_FUNC_BOOT_ENA); 310 } 311 312 void iwl_pcie_ctxt_info_v2_free(struct iwl_trans *trans, bool alive) 313 { 314 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 315 316 if (trans_pcie->iml) { 317 dma_free_coherent(trans->dev, trans_pcie->iml_len, 318 trans_pcie->iml, 319 trans_pcie->iml_dma_addr); 320 trans_pcie->iml_dma_addr = 0; 321 trans_pcie->iml_len = 0; 322 trans_pcie->iml = NULL; 323 } 324 325 iwl_pcie_ctxt_info_free_fw_img(trans); 326 327 if (alive) 328 return; 329 330 if (!trans_pcie->ctxt_info_v2) 331 return; 332 333 /* ctxt_info_v2 and prph_scratch are still needed for PNVM load */ 334 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_v2), 335 trans_pcie->ctxt_info_v2, 336 trans_pcie->ctxt_info_dma_addr); 337 trans_pcie->ctxt_info_dma_addr = 0; 338 trans_pcie->ctxt_info_v2 = NULL; 339 340 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 341 trans_pcie->prph_scratch, 342 trans_pcie->prph_scratch_dma_addr); 343 trans_pcie->prph_scratch_dma_addr = 0; 344 trans_pcie->prph_scratch = NULL; 345 346 /* this is needed for the entire lifetime */ 347 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info, 348 trans_pcie->prph_info_dma_addr); 349 trans_pcie->prph_info_dma_addr = 0; 350 trans_pcie->prph_info = NULL; 351 } 352 353 static int iwl_pcie_load_payloads_contig(struct iwl_trans *trans, 354 const struct iwl_pnvm_image *pnvm_data, 355 struct iwl_dram_data *dram) 356 { 357 u32 len, len0, len1; 358 359 if (pnvm_data->n_chunks != UNFRAGMENTED_PNVM_PAYLOADS_NUMBER) { 360 IWL_DEBUG_FW(trans, "expected 2 payloads, got %d.\n", 361 pnvm_data->n_chunks); 362 return -EINVAL; 363 } 364 365 len0 = pnvm_data->chunks[0].len; 366 len1 = pnvm_data->chunks[1].len; 367 if (len1 > 0xFFFFFFFF - len0) { 368 IWL_DEBUG_FW(trans, "sizes of payloads overflow.\n"); 369 return -EINVAL; 370 } 371 len = len0 + len1; 372 373 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, 374 &dram->physical); 375 if (!dram->block) { 376 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n"); 377 return -ENOMEM; 378 } 379 380 dram->size = len; 381 memcpy(dram->block, pnvm_data->chunks[0].data, len0); 382 memcpy((u8 *)dram->block + len0, pnvm_data->chunks[1].data, len1); 383 384 return 0; 385 } 386 387 static int iwl_pcie_load_payloads_segments 388 (struct iwl_trans *trans, 389 struct iwl_dram_regions *dram_regions, 390 const struct iwl_pnvm_image *pnvm_data) 391 { 392 struct iwl_dram_data *cur_payload_dram = &dram_regions->drams[0]; 393 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 394 struct iwl_prph_scrath_mem_desc_addr_array *addresses; 395 const void *data; 396 u32 len; 397 int i; 398 399 /* allocate and init DRAM descriptors array */ 400 len = sizeof(struct iwl_prph_scrath_mem_desc_addr_array); 401 desc_dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent 402 (trans, 403 len, 404 &desc_dram->physical); 405 if (!desc_dram->block) { 406 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n"); 407 return -ENOMEM; 408 } 409 desc_dram->size = len; 410 memset(desc_dram->block, 0, len); 411 412 /* allocate DRAM region for each payload */ 413 dram_regions->n_regions = 0; 414 for (i = 0; i < pnvm_data->n_chunks; i++) { 415 len = pnvm_data->chunks[i].len; 416 data = pnvm_data->chunks[i].data; 417 418 if (iwl_pcie_ctxt_info_alloc_dma(trans, 419 data, 420 len, 421 cur_payload_dram)) { 422 iwl_trans_pcie_free_pnvm_dram_regions(dram_regions, 423 trans->dev); 424 return -ENOMEM; 425 } 426 427 dram_regions->n_regions++; 428 cur_payload_dram++; 429 } 430 431 /* fill desc with the DRAM payloads addresses */ 432 addresses = desc_dram->block; 433 for (i = 0; i < pnvm_data->n_chunks; i++) { 434 addresses->mem_descs[i] = 435 cpu_to_le64(dram_regions->drams[i].physical); 436 } 437 438 return 0; 439 440 } 441 442 int iwl_trans_pcie_ctx_info_v2_load_pnvm(struct iwl_trans *trans, 443 const struct iwl_pnvm_image *pnvm_payloads, 444 const struct iwl_ucode_capabilities *capa) 445 { 446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 447 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 448 &trans_pcie->prph_scratch->ctrl_cfg; 449 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; 450 int ret = 0; 451 452 /* only allocate the DRAM if not allocated yet */ 453 if (trans->pnvm_loaded) 454 return 0; 455 456 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) 457 return -EBUSY; 458 459 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 460 return 0; 461 462 if (!pnvm_payloads->n_chunks) { 463 IWL_DEBUG_FW(trans, "no payloads\n"); 464 return -EINVAL; 465 } 466 467 /* save payloads in several DRAM sections */ 468 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) { 469 ret = iwl_pcie_load_payloads_segments(trans, 470 dram_regions, 471 pnvm_payloads); 472 if (!ret) 473 trans->pnvm_loaded = true; 474 } else { 475 /* save only in one DRAM section */ 476 ret = iwl_pcie_load_payloads_contig(trans, pnvm_payloads, 477 &dram_regions->drams[0]); 478 if (!ret) { 479 dram_regions->n_regions = 1; 480 trans->pnvm_loaded = true; 481 } 482 } 483 484 return ret; 485 } 486 487 static inline size_t 488 iwl_dram_regions_size(const struct iwl_dram_regions *dram_regions) 489 { 490 size_t total_size = 0; 491 int i; 492 493 for (i = 0; i < dram_regions->n_regions; i++) 494 total_size += dram_regions->drams[i].size; 495 496 return total_size; 497 } 498 499 static void iwl_pcie_set_pnvm_segments(struct iwl_trans *trans) 500 { 501 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 502 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 503 &trans_pcie->prph_scratch->ctrl_cfg; 504 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; 505 506 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 507 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); 508 prph_sc_ctrl->pnvm_cfg.pnvm_size = 509 cpu_to_le32(iwl_dram_regions_size(dram_regions)); 510 } 511 512 static void iwl_pcie_set_contig_pnvm(struct iwl_trans *trans) 513 { 514 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 515 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 516 &trans_pcie->prph_scratch->ctrl_cfg; 517 518 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 519 cpu_to_le64(trans_pcie->pnvm_data.drams[0].physical); 520 prph_sc_ctrl->pnvm_cfg.pnvm_size = 521 cpu_to_le32(trans_pcie->pnvm_data.drams[0].size); 522 } 523 524 void iwl_trans_pcie_ctx_info_v2_set_pnvm(struct iwl_trans *trans, 525 const struct iwl_ucode_capabilities *capa) 526 { 527 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 528 return; 529 530 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) 531 iwl_pcie_set_pnvm_segments(trans); 532 else 533 iwl_pcie_set_contig_pnvm(trans); 534 } 535 536 int iwl_trans_pcie_ctx_info_v2_load_reduce_power(struct iwl_trans *trans, 537 const struct iwl_pnvm_image *payloads, 538 const struct iwl_ucode_capabilities *capa) 539 { 540 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 541 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 542 &trans_pcie->prph_scratch->ctrl_cfg; 543 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; 544 int ret = 0; 545 546 /* only allocate the DRAM if not allocated yet */ 547 if (trans->reduce_power_loaded) 548 return 0; 549 550 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 551 return 0; 552 553 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) 554 return -EBUSY; 555 556 if (!payloads->n_chunks) { 557 IWL_DEBUG_FW(trans, "no payloads\n"); 558 return -EINVAL; 559 } 560 561 /* save payloads in several DRAM sections */ 562 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) { 563 ret = iwl_pcie_load_payloads_segments(trans, 564 dram_regions, 565 payloads); 566 if (!ret) 567 trans->reduce_power_loaded = true; 568 } else { 569 /* save only in one DRAM section */ 570 ret = iwl_pcie_load_payloads_contig(trans, payloads, 571 &dram_regions->drams[0]); 572 if (!ret) { 573 dram_regions->n_regions = 1; 574 trans->reduce_power_loaded = true; 575 } 576 } 577 578 return ret; 579 } 580 581 static void iwl_pcie_set_reduce_power_segments(struct iwl_trans *trans) 582 { 583 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 584 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 585 &trans_pcie->prph_scratch->ctrl_cfg; 586 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; 587 588 prph_sc_ctrl->reduce_power_cfg.base_addr = 589 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); 590 prph_sc_ctrl->reduce_power_cfg.size = 591 cpu_to_le32(iwl_dram_regions_size(dram_regions)); 592 } 593 594 static void iwl_pcie_set_contig_reduce_power(struct iwl_trans *trans) 595 { 596 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 597 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 598 &trans_pcie->prph_scratch->ctrl_cfg; 599 600 prph_sc_ctrl->reduce_power_cfg.base_addr = 601 cpu_to_le64(trans_pcie->reduced_tables_data.drams[0].physical); 602 prph_sc_ctrl->reduce_power_cfg.size = 603 cpu_to_le32(trans_pcie->reduced_tables_data.drams[0].size); 604 } 605 606 void 607 iwl_trans_pcie_ctx_info_v2_set_reduce_power(struct iwl_trans *trans, 608 const struct iwl_ucode_capabilities *capa) 609 { 610 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 611 return; 612 613 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) 614 iwl_pcie_set_reduce_power_segments(trans); 615 else 616 iwl_pcie_set_contig_reduce_power(trans); 617 } 618 619