1[ 2 { 3 "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", 4 "Counter": "0", 5 "EventCode": "0xff", 6 "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", 7 "PerPkg": "1", 8 "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", 9 "UMask": "0x20", 10 "Unit": "imc_free_running_0" 11 }, 12 { 13 "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 14 "Counter": "1", 15 "EventCode": "0xff", 16 "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", 17 "PerPkg": "1", 18 "UMask": "0x30", 19 "Unit": "imc_free_running_0" 20 }, 21 { 22 "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", 23 "Counter": "3", 24 "EventCode": "0xff", 25 "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", 26 "PerPkg": "1", 27 "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", 28 "UMask": "0x20", 29 "Unit": "imc_free_running_1" 30 }, 31 { 32 "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 33 "Counter": "4", 34 "EventCode": "0xff", 35 "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", 36 "PerPkg": "1", 37 "UMask": "0x30", 38 "Unit": "imc_free_running_1" 39 }, 40 { 41 "BriefDescription": "ACT command for a read request sent to DRAM", 42 "Counter": "0,1,2,3,4", 43 "EventCode": "0x24", 44 "EventName": "UNC_M_ACT_COUNT_RD", 45 "PerPkg": "1", 46 "Unit": "iMC" 47 }, 48 { 49 "BriefDescription": "ACT command sent to DRAM", 50 "Counter": "0,1,2,3,4", 51 "EventCode": "0x26", 52 "EventName": "UNC_M_ACT_COUNT_TOTAL", 53 "PerPkg": "1", 54 "Unit": "iMC" 55 }, 56 { 57 "BriefDescription": "ACT command for a write request sent to DRAM", 58 "Counter": "0,1,2,3,4", 59 "EventCode": "0x25", 60 "EventName": "UNC_M_ACT_COUNT_WR", 61 "PerPkg": "1", 62 "Unit": "iMC" 63 }, 64 { 65 "BriefDescription": "Read CAS command sent to DRAM", 66 "Counter": "0,1,2,3,4", 67 "EventCode": "0x22", 68 "EventName": "UNC_M_CAS_COUNT_RD", 69 "PerPkg": "1", 70 "Unit": "iMC" 71 }, 72 { 73 "BriefDescription": "Write CAS command sent to DRAM", 74 "Counter": "0,1,2,3,4", 75 "EventCode": "0x23", 76 "EventName": "UNC_M_CAS_COUNT_WR", 77 "PerPkg": "1", 78 "Unit": "iMC" 79 }, 80 { 81 "BriefDescription": "Number of clocks", 82 "Counter": "0,1,2,3,4", 83 "EventCode": "0x01", 84 "EventName": "UNC_M_CLOCKTICKS", 85 "PerPkg": "1", 86 "Unit": "iMC" 87 }, 88 { 89 "BriefDescription": "incoming read request page status is Page Empty", 90 "Counter": "0,1,2,3,4", 91 "EventCode": "0x1D", 92 "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", 93 "PerPkg": "1", 94 "Unit": "iMC" 95 }, 96 { 97 "BriefDescription": "incoming write request page status is Page Empty", 98 "Counter": "0,1,2,3,4", 99 "EventCode": "0x20", 100 "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", 101 "PerPkg": "1", 102 "Unit": "iMC" 103 }, 104 { 105 "BriefDescription": "incoming read request page status is Page Hit", 106 "Counter": "0,1,2,3,4", 107 "EventCode": "0x1C", 108 "EventName": "UNC_M_DRAM_PAGE_HIT_RD", 109 "PerPkg": "1", 110 "Unit": "iMC" 111 }, 112 { 113 "BriefDescription": "incoming write request page status is Page Hit", 114 "Counter": "0,1,2,3,4", 115 "EventCode": "0x1F", 116 "EventName": "UNC_M_DRAM_PAGE_HIT_WR", 117 "PerPkg": "1", 118 "Unit": "iMC" 119 }, 120 { 121 "BriefDescription": "incoming read request page status is Page Miss", 122 "Counter": "0,1,2,3,4", 123 "EventCode": "0x1E", 124 "EventName": "UNC_M_DRAM_PAGE_MISS_RD", 125 "PerPkg": "1", 126 "Unit": "iMC" 127 }, 128 { 129 "BriefDescription": "incoming write request page status is Page Miss", 130 "Counter": "0,1,2,3,4", 131 "EventCode": "0x21", 132 "EventName": "UNC_M_DRAM_PAGE_MISS_WR", 133 "PerPkg": "1", 134 "Unit": "iMC" 135 }, 136 { 137 "BriefDescription": "Any Rank at Hot state", 138 "Counter": "0,1,2,3,4", 139 "EventCode": "0x19", 140 "EventName": "UNC_M_DRAM_THERMAL_HOT", 141 "PerPkg": "1", 142 "Unit": "iMC" 143 }, 144 { 145 "BriefDescription": "Any Rank at Warm state", 146 "Counter": "0,1,2,3,4", 147 "EventCode": "0x1A", 148 "EventName": "UNC_M_DRAM_THERMAL_WARM", 149 "PerPkg": "1", 150 "Unit": "iMC" 151 }, 152 { 153 "BriefDescription": "Incoming read prefetch request from IA.", 154 "Counter": "0,1,2,3,4", 155 "EventCode": "0x0A", 156 "EventName": "UNC_M_PREFETCH_RD", 157 "PerPkg": "1", 158 "Unit": "iMC" 159 }, 160 { 161 "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", 162 "Counter": "0,1,2,3,4", 163 "EventCode": "0x28", 164 "EventName": "UNC_M_PRE_COUNT_IDLE", 165 "PerPkg": "1", 166 "Unit": "iMC" 167 }, 168 { 169 "BriefDescription": "PRE command sent to DRAM for a read/write request", 170 "Counter": "0,1,2,3,4", 171 "EventCode": "0x27", 172 "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", 173 "PerPkg": "1", 174 "Unit": "iMC" 175 }, 176 { 177 "BriefDescription": "Incoming VC0 read request", 178 "Counter": "0,1,2,3,4", 179 "EventCode": "0x02", 180 "EventName": "UNC_M_VC0_REQUESTS_RD", 181 "PerPkg": "1", 182 "Unit": "iMC" 183 }, 184 { 185 "BriefDescription": "Incoming VC0 write request", 186 "Counter": "0,1,2,3,4", 187 "EventCode": "0x03", 188 "EventName": "UNC_M_VC0_REQUESTS_WR", 189 "PerPkg": "1", 190 "Unit": "iMC" 191 }, 192 { 193 "BriefDescription": "Incoming VC1 read request", 194 "Counter": "0,1,2,3,4", 195 "EventCode": "0x04", 196 "EventName": "UNC_M_VC1_REQUESTS_RD", 197 "PerPkg": "1", 198 "Unit": "iMC" 199 }, 200 { 201 "BriefDescription": "Incoming VC1 write request", 202 "Counter": "0,1,2,3,4", 203 "EventCode": "0x05", 204 "EventName": "UNC_M_VC1_REQUESTS_WR", 205 "PerPkg": "1", 206 "Unit": "iMC" 207 } 208] 209