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/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c105 * Covers frequency and voltage settings of the DMC operating mode.
113 * struct exynos5_dmc - main structure describing DMC device
114 * @dev: DMC device
239 static int exynos5_counters_set_event(struct exynos5_dmc *dmc) in exynos5_counters_set_event() argument
243 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
244 if (!dmc->counter[i]) in exynos5_counters_set_event()
246 ret = devfreq_event_set_event(dmc->counter[i]); in exynos5_counters_set_event()
253 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) in exynos5_counters_enable_edev() argument
257 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_enable_edev()
258 if (!dmc->counter[i]) in exynos5_counters_enable_edev()
[all …]
H A DKconfig17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory
19 Frequency Scaling in DMC and DRAM. It also supports changing timings
H A DMakefile2 obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dmc.c46 * DOC: DMC Firmware Support
48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
89 return display->dmc.dmc; in display_to_dmc()
115 * New DMC additions should not use this. This is used solely to remain
116 * compatible with systems that have not yet updated DMC blobs to use
263 /* 0x09 for DMC */
266 /* Includes the DMC specific header in dwords */
281 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
323 /* DMC containe
405 struct intel_dmc *dmc = display_to_dmc(display); has_dmc_id_fw() local
608 dmc_mmiodata(struct intel_display * display,struct intel_dmc * dmc,enum intel_dmc_id dmc_id,int i) dmc_mmiodata() argument
621 struct intel_dmc *dmc = display_to_dmc(display); dmc_load_mmio() local
632 struct intel_dmc *dmc = display_to_dmc(display); dmc_load_program() local
653 struct intel_dmc *dmc = display_to_dmc(display); assert_dmc_loaded() local
820 struct intel_dmc *dmc = display_to_dmc(display); dmc_configure_event() local
957 dmc_set_fw_offset(struct intel_dmc * dmc,const struct intel_fw_info * fw_info,unsigned int num_entries,const struct stepping_info * si,u8 package_ver) dmc_set_fw_offset() argument
989 dmc_mmio_addr_sanity_check(struct intel_dmc * dmc,const u32 * mmioaddr,u32 mmio_count,int header_ver,enum intel_dmc_id dmc_id) dmc_mmio_addr_sanity_check() argument
1022 parse_dmc_fw_header(struct intel_dmc * dmc,const struct intel_dmc_header_base * dmc_header,size_t rem_size,enum intel_dmc_id dmc_id) parse_dmc_fw_header() argument
1163 parse_dmc_fw_package(struct intel_dmc * dmc,const struct intel_package_header * package_header,const struct stepping_info * si,size_t rem_size) parse_dmc_fw_package() argument
1218 parse_dmc_fw_css(struct intel_dmc * dmc,struct intel_css_header * css_header,size_t rem_size) parse_dmc_fw_css() argument
1242 parse_dmc_fw(struct intel_dmc * dmc,const struct firmware * fw) parse_dmc_fw() argument
1319 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); dmc_load_work_fn() local
1375 struct intel_dmc *dmc; intel_dmc_init() local
1435 struct intel_dmc *dmc = display_to_dmc(display); intel_dmc_suspend() local
1450 struct intel_dmc *dmc = display_to_dmc(display); intel_dmc_wait_fw_load() local
1488 struct intel_dmc *dmc = display_to_dmc(display); intel_dmc_fini() local
1514 struct intel_dmc *dmc = display_to_dmc(display); intel_dmc_snapshot_capture() local
1548 struct intel_dmc *dmc = display_to_dmc(display); intel_dmc_update_dc6_allowed_count() local
1565 struct intel_dmc *dmc = display_to_dmc(display); intel_dmc_get_dc6_allowed_count() local
1586 struct intel_dmc *dmc = display_to_dmc(display); intel_dmc_debugfs_status_show() local
1731 struct intel_dmc *dmc = display_to_dmc(display); intel_pipedmc_start_mmioaddr() local
[all...]
H A Dintel_display_power.c977 * not depending on the DMC firmware. It's needed by system in get_allowed_dc_mask()
1498 /* TODO: disable DMC program */ in skl_display_core_uninit()
1513 * may stay enabled after this due to DMC's own request on it. in skl_display_core_uninit()
1566 /* TODO: disable DMC program */ in bxt_display_core_uninit()
1577 * may stay enabled after this due to DMC's own request on it. in bxt_display_core_uninit()
2115 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 in intel_power_domains_suspend()
2117 * DMC firmware will stay active, it will power down any HW in intel_power_domains_suspend()
/linux/Documentation/devicetree/bindings/edac/
H A Ddmc-520.yaml4 $id: http://devicetree.org/schemas/edac/dmc-520.yaml#
7 title: ARM DMC-520 EDAC
13 DMC-520 node is defined to describe DRAM error detection and correction.
20 - const: brcm,dmc-520
21 - const: arm,dmc-520
56 dmc0: dmc@200000 {
57 compatible = "brcm,dmc-520", "arm,dmc-520";
/linux/Documentation/admin-guide/perf/
H A Dthunderx2-pmu.rst6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dsamsung,exynos5422-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
22 switch the DMC and memory frequency.
27 - const: samsung,exynos5422-dmc
62 - description: DMC internal performance event counters in DREX0
63 - description: DMC internal performance event counters in DREX1
112 compatible = "samsung,exynos5422-dmc";
H A Dsamsung,s5pv210-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/samsung,s5pv210-dmc.yaml#
17 const: samsung,s5pv210-dmc
31 compatible = "samsung,s5pv210-dmc";
H A Drockchip,rk3399-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
15 - rockchip,rk3399-dmc
34 DMC regulator supply.
363 compatible = "rockchip,rk3399-dmc";
/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml49 VDD_MIF |--- DMC (Dynamic Memory Controller)
93 VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
110 VDD_MIF |--- DMC (Dynamic Memory Controller)
225 bus-dmc {
287 dmc: bus-dmc {
303 interconnects = <&dmc>;
314 interconnects = <&leftbus &dmc>;
/linux/include/soc/amlogic/
H A Dmeson_ddr_pmu.h35 u64 channel_cnt[MAX_CHANNEL_NUM]; /* To save a DMC bandwidth-monitor channel counter */
48 int dmc_nr; /* The number of dmc controller */
49 int chann_nr; /* The number of dmc bandwidth monitor channels */
/linux/drivers/net/ethernet/sun/
H A Dniu.h19 #define DMC 0x600000UL macro
1978 #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
1984 #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
1990 #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
1996 #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
2026 #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
2029 #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
2032 #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
2035 #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
2038 #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
[all …]
/linux/drivers/acpi/apei/
H A Dhest.c51 struct acpi_hest_ia_deferred_check *dmc; member
99 mces.dmc = mc; in hest_esrc_len()
128 if (mces.dmc && mces.dmc->flags & ACPI_HEST_GHES_ASSIST && in is_ghes_assist_struct()
129 related_source_id == mces.dmc->header.source_id) in is_ghes_assist_struct()
/linux/Documentation/devicetree/bindings/perf/
H A Damlogic,g12-ddr-pmu.yaml27 - description: DMC bandwidth register space.
28 - description: DMC PLL register space.
/linux/drivers/edac/
H A Ddmc520_edac.c4 * EDAC driver for DMC-520 memory controller.
25 /* DMC-520 registers */
43 /* DMC-520 types, masks and bitfields */
630 { .compatible = "arm,dmc-520", },
651 MODULE_DESCRIPTION("DMC-520 ECC driver");
/linux/drivers/perf/
H A DKconfig218 in the DDR4 Memory Controller (DMC).
247 tristate "Enable PMU support for the ARM DMC-620 memory controller"
250 Support for PMU events monitoring on the ARM DMC-620 memory
/linux/drivers/devfreq/
H A DKconfig144 tristate "ARM RK3399 DMC DEVFREQ Driver"
151 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
H A Drk3399_dmc.c470 { .compatible = "rockchip,rk3399-dmc" },
479 .name = "rk3399-dmc-freq",
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi500 dmc0: dmc@f0000000 {
501 compatible = "samsung,s5pv210-dmc";
505 dmc1: dmc@f1400000 {
506 compatible = "samsung,s5pv210-dmc";
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos-clock.yaml24 - samsung,exynos3250-cmu-dmc
/linux/Documentation/gpu/
H A Dmeson.rst16 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
/linux/Documentation/translations/zh_CN/filesystems/
H A Dubifs-authentication.rst27 进制文件使其执行时触发恶意行为 [DMC-CBC-ATTACK]。由于 UBIFS 大部分文件
345 [DMC-CBC-ATTACK] https://www.jakoblell.com/blog/2013/12/22/practical-malleability-attack-agains…
/linux/Documentation/devicetree/bindings/devfreq/event/
H A Dsamsung,exynos-ppmu.yaml18 each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-op1.dtsi162 &dmc {

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