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/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c105 * Covers frequency and voltage settings of the DMC operating mode.
113 * struct exynos5_dmc - main structure describing DMC device
114 * @dev: DMC device
239 static int exynos5_counters_set_event(struct exynos5_dmc *dmc) in exynos5_counters_set_event() argument
243 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
244 if (!dmc->counter[i]) in exynos5_counters_set_event()
246 ret = devfreq_event_set_event(dmc->counter[i]); in exynos5_counters_set_event()
253 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) in exynos5_counters_enable_edev() argument
257 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_enable_edev()
258 if (!dmc->counter[i]) in exynos5_counters_enable_edev()
[all …]
H A DKconfig17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory
19 Frequency Scaling in DMC and DRAM. It also supports changing timings
H A DMakefile2 obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dmc.c46 * DOC: DMC Firmware Support
48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
89 return display->dmc.dmc; in display_to_dmc()
115 * New DMC additions should not use this. This is used solely to remain
116 * compatible with systems that have not yet updated DMC blobs to use
263 /* 0x09 for DMC */
266 /* Includes the DMC specific header in dwords */
281 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
323 /* DMC container header length in dwords */
339 /* DMC binary header length */
[all …]
H A Dintel_display_snapshot.c23 struct intel_dmc_snapshot *dmc; member
45 snapshot->dmc = intel_dmc_snapshot_capture(display); in intel_display_snapshot_capture()
65 intel_dmc_snapshot_print(snapshot->dmc, p); in intel_display_snapshot_print()
77 kfree(snapshot->dmc); in intel_display_snapshot_free()
H A Dintel_display_power_map.c358 /* Handled by the DMC firmware */
372 /* Handled by the DMC firmware */
611 * ICL PW_0/PG_0 domains (HW/DMC control):
616 * ICL PW_1/PG_1 domains (HW/DMC control):
717 /* Handled by the DMC firmware */
1034 * RKL PW_1/PG_1 domains (under HW/DMC control):
1041 * RKL PW_0/PG_0 domains (under HW/DMC control):
1283 * XELPD PW_1/PG_1 domains (under HW/DMC control):
1288 * XELPD PW_0/PW_1 domains (under HW/DMC control):
H A Dintel_display_power_well.c350 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and in hsw_wait_for_power_well_disable()
629 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 in hsw_power_well_enabled()
694 * doesn't stick and dmc keeps returning old value. Make sure in gen9_write_dc_state()
767 * Signal to DMC firmware/HW the target DC power state passed in @state.
768 * DMC/HW can turn off individual display clocks and power rails when entering
803 /* Check if DMC is ignoring our DC state requests */ in gen9_set_dc_state()
1050 * DMC retains HW context only for port A, the other combo in gen9_disable_dc_states()
/linux/Documentation/devicetree/bindings/edac/
H A Ddmc-520.yaml4 $id: http://devicetree.org/schemas/edac/dmc-520.yaml#
7 title: ARM DMC-520 EDAC
13 DMC-520 node is defined to describe DRAM error detection and correction.
20 - const: brcm,dmc-520
21 - const: arm,dmc-520
56 dmc0: dmc@200000 {
57 compatible = "brcm,dmc-520", "arm,dmc-520";
/linux/Documentation/admin-guide/perf/
H A Dthunderx2-pmu.rst6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dsamsung,exynos5422-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
22 switch the DMC and memory frequency.
27 - const: samsung,exynos5422-dmc
62 - description: DMC internal performance event counters in DREX0
63 - description: DMC internal performance event counters in DREX1
112 compatible = "samsung,exynos5422-dmc";
H A Dsamsung,s5pv210-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/samsung,s5pv210-dmc.yaml#
17 const: samsung,s5pv210-dmc
31 compatible = "samsung,s5pv210-dmc";
H A Drockchip,rk3399-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
15 - rockchip,rk3399-dmc
34 DMC regulator supply.
363 compatible = "rockchip,rk3399-dmc";
/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml49 VDD_MIF |--- DMC (Dynamic Memory Controller)
93 VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
110 VDD_MIF |--- DMC (Dynamic Memory Controller)
225 bus-dmc {
287 dmc: bus-dmc {
303 interconnects = <&dmc>;
314 interconnects = <&leftbus &dmc>;
/linux/include/soc/amlogic/
H A Dmeson_ddr_pmu.h35 u64 channel_cnt[MAX_CHANNEL_NUM]; /* To save a DMC bandwidth-monitor channel counter */
48 int dmc_nr; /* The number of dmc controller */
49 int chann_nr; /* The number of dmc bandwidth monitor channels */
/linux/drivers/net/ethernet/sun/
H A Dniu.h19 #define DMC 0x600000UL macro
1978 #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
1984 #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
1990 #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
1996 #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
2026 #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
2029 #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
2032 #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
2035 #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
2038 #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
[all …]
/linux/drivers/acpi/apei/
H A Dhest.c51 struct acpi_hest_ia_deferred_check *dmc; member
99 mces.dmc = mc; in hest_esrc_len()
128 if (mces.dmc && mces.dmc->flags & ACPI_HEST_GHES_ASSIST && in is_ghes_assist_struct()
129 related_source_id == mces.dmc->header.source_id) in is_ghes_assist_struct()
/linux/Documentation/devicetree/bindings/perf/
H A Damlogic,g12-ddr-pmu.yaml27 - description: DMC bandwidth register space.
28 - description: DMC PLL register space.
/linux/drivers/edac/
H A Ddmc520_edac.c4 * EDAC driver for DMC-520 memory controller.
25 /* DMC-520 registers */
43 /* DMC-520 types, masks and bitfields */
630 { .compatible = "arm,dmc-520", },
651 MODULE_DESCRIPTION("DMC-520 ECC driver");
/linux/drivers/perf/
H A DKconfig218 in the DDR4 Memory Controller (DMC).
247 tristate "Enable PMU support for the ARM DMC-620 memory controller"
250 Support for PMU events monitoring on the ARM DMC-620 memory
H A Darm_dmc620_pmu.c3 * ARM DMC-620 memory controller PMU driver
40 * The PMU registers start at 0xA00 in the DMC-620 memory map, and these
522 * DMC 620 PMUs are shared across all cpus and cannot in dmc620_pmu_event_init()
783 MODULE_DESCRIPTION("Perf driver for the ARM DMC-620 memory controller");
/linux/drivers/devfreq/
H A DKconfig144 tristate "ARM RK3399 DMC DEVFREQ Driver"
151 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi500 dmc0: dmc@f0000000 {
501 compatible = "samsung,s5pv210-dmc";
505 dmc1: dmc@f1400000 {
506 compatible = "samsung,s5pv210-dmc";
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos-clock.yaml24 - samsung,exynos3250-cmu-dmc
/linux/Documentation/gpu/
H A Dmeson.rst16 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
/linux/Documentation/translations/zh_CN/filesystems/
H A Dubifs-authentication.rst27 进制文件使其执行时触发恶意行为 [DMC-CBC-ATTACK]。由于 UBIFS 大部分文件
345 [DMC-CBC-ATTACK] https://www.jakoblell.com/blog/2013/12/22/practical-malleability-attack-agains…

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