| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-st.txt | 57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
109 sd-uhs-ddr50;
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| H A D | sdhci-am654.yaml | 103 ti,otap-del-sel-ddr50:
104 description: Output tap delay for SD UHS DDR50 timing
161 ti,itap-del-sel-ddr50:
162 description: Input tap delay for MMC DDR50 timing
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| H A D | sdhci-omap.txt | 19 "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
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| H A D | cdns,sdhci.yaml | 71 cdns,phy-input-delay-sd-uhs-ddr50:
72 description: Value of the delay in the input path for SD UHS DDR50 timing
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stih418-b2199.dts | 94 sd-uhs-ddr50;
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | dra72x-mmc-iodelay.dtsi | 17 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
90 mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins {
101 mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins {
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| H A D | dra72-evm.dts | 94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra72-evm-revc.dts | 124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra76x-mmc-iodelay.dtsi | 15 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
63 mmc1_pins_ddr50: mmc1-ddr50-pins {
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| H A D | dra7-evm.dts | 389 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
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| H A D | dra74x-mmc-iodelay.dtsi | 17 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
88 mmc1_pins_ddr50: mmc1-ddr50-pins {
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| H A D | am5729-beagleboneai.dts | 561 /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
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| /linux/arch/arm64/boot/dts/amd/ |
| H A D | elba.dtsi | 181 cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
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| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-gxl-s905x-libretech-cc-v2.dts | 254 sd-uhs-ddr50;
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| H A D | meson-gx-libretech-pc.dtsi | 379 sd-uhs-ddr50;
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| H A D | meson-gxbb-nanopi-k2.dts | 350 sd-uhs-ddr50;
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| /linux/drivers/mmc/host/ |
| H A D | sdhci-of-sparx5.c | 154 SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
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| H A D | owl-mmc.c | 411 /* DDR50 mode has special delay chain */ in owl_mmc_set_clk_rate()
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| /linux/drivers/mmc/core/ |
| H A D | debugfs.c | 145 str = "sd uhs DDR50"; in mmc_ios_show()
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qdl-skov-cpu.dtsi | 336 sd-uhs-ddr50;
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| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 114 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
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| H A D | armada-8040-puzzle-m801.dts | 148 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
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| /linux/include/linux/mmc/ |
| H A D | card.h | 332 #define MMC_QUIRK_NO_UHS_DDR50_TUNING (1<<18) /* Disable DDR50 tuning */
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| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | msm8916-samsung-serranove.dts | 398 * a hardware limitation. However, probing a card using DDR50 works
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| /linux/arch/powerpc/boot/dts/ |
| H A D | fsp2.dts | 506 sd-uhs-ddr50;
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