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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
20 Node to get DDR loading. Refer to
26 clock-names:
28 - const: dmc_clk
[all …]
/linux/drivers/soc/qcom/
H A Dqcom_stats.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2025, Qualcomm Innovation Center, Inc. All rights reserved.
100 u64 accumulated = stat->accumulated; in qcom_print_stats()
105 if (stat->last_entered_at > stat->last_exited_at) in qcom_print_stats()
106 accumulated += arch_timer_read_counter() - stat->last_entered_at; in qcom_print_stats()
108 seq_printf(s, "Count: %u\n", stat->count); in qcom_print_stats()
109 seq_printf(s, "Last Entered At: %llu\n", stat->last_entered_at); in qcom_print_stats()
110 seq_printf(s, "Last Exited At: %llu\n", stat->last_exited_at); in qcom_print_stats()
116 struct subsystem_data *subsystem = s->private; in qcom_subsystem_sleep_stats_show()
[all …]
/linux/drivers/edac/
H A Dsynopsys_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys DDR ECC Driver
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
33 /* Synopsys DDR memory controller registers that are relevant to ECC */
89 /* DDR ECC Quirks */
94 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
143 /* DDR Control Register width definitions */
160 /* DDR QOS Interrupt register definitions */
168 /* DDR QOS Interrupt register definitions */
193 /* DDR Memory type defines */
[all …]
H A Dhighbank_mc_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
17 /* DDR Ctrlr Error Registers */
36 /* DDR Ctrlr Interrupt Registers */
57 struct hb_mc_drvdata *drvdata = mci->pvt_info; in highbank_mc_err_handler()
61 status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS); in highbank_mc_err_handler()
64 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR); in highbank_mc_err_handler()
68 0, 0, -1, in highbank_mc_err_handler()
69 mci->ctl_name, ""); in highbank_mc_err_handler()
72 u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT); in highbank_mc_err_handler()
[all …]
H A Dversal_edac.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/firmware/xlnx-zynqmp.h>
16 #include <linux/firmware/xlnx-event-manager.h>
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
149 * struct ecc_error_info - ECC error log information.
195 * struct ecc_status - ECC status information to report.
199 * @error_type: Error type information.
209 * struct edac_priv - DDR memory controller private instance data.
210 * @ddrmc_baseaddr: Base address of the DDR controller.
255 ddrmc_base = priv->ddrmc_baseaddr; in get_ce_error_info()
[all …]
/linux/drivers/memory/
H A Dof_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * of_get_min_tck() - extract min timing values for ddr
20 * @np: pointer to ddr device tree node
38 ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); in of_get_min_tck()
39 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_get_min_tck()
40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
41 ret |= of_property_read_u32(np, "tRASmin-min-tck", &min->tRASmin); in of_get_min_tck()
42 ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); in of_get_min_tck()
43 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_get_min_tck()
44 ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); in of_get_min_tck()
[all …]
H A Djedec_ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Definitions for DDR memories based on JEDEC specs
14 /* DDR Densities */
26 /* DDR type */
34 /* DDR IO width */
64 /* Refresh rate in nano-seconds */
135 /* Structure for DDR addressing info from the JEDEC spec */
171 * type
207 * -ENOENT if info unavailable.
254 * type
H A Demif.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * struct emif_data - Per device static data for driver's use
34 * @duplicate: Whether the DDR devices attached to this EMIF
38 * to this EMIF - read from MR4 register. If there
44 * @base: base address of memory-mapped IO registers.
48 * frequencies, to avoid re-calculating them on
55 * @np_ddr: Pointer to ddr device tree node
78 u32 type = emif->plat_data->device_info->type; in do_emif_regdump_show() local
79 u32 ip_rev = emif->plat_data->ip_rev; in do_emif_regdump_show()
82 regs->freq/1000000); in do_emif_regdump_show()
[all …]
H A Drenesas-rpc-if.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RPC-IF core driver
5 * Copyright (C) 2018-2019 Renesas Solutions Corp.
7 * Copyright (C) 2019-2020 Cogent Embedded, Inc.
19 #include <memory/renesas-rpc-if.h>
21 #include "renesas-rpc-if-regs.h"
22 #include "renesas-xspi-if-regs.h"
60 enum rpcif_type type; member
88 u32 ddr; /* DRDRENR or SMDRENR */ member
102 switch (rpc->xfer_size) { in rpcif_reg_read()
[all …]
/linux/drivers/iio/dac/
H A Dad3552r-hs.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include "ad3552r-hs.h"
39 * Also, important to note that none of the three modes allow to read in DDR.
41 * In non-buffering operations, mode is set to simple SPI SDR for all primary
44 * content (possible as non DDR only).
45 * In buffering mode, driver sets best possible mode, D/QSPI and DDR.
56 /* INTERFACE_CONFIG_D register cache, in DDR we cannot read values. */
69 [AD3552R_SRC_RAMP_16BIT] = "ramp-16bit",
75 /* No chip in the family supports DDR read. Informing of this. */ in ad3552r_hs_reg_read()
76 WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR); in ad3552r_hs_reg_read()
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-channel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
26 io-width:
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Drohm,bd9571mwv.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marek.vasut@gmail.com>
15 - rohm,bd9571mwv
16 - rohm,bd9574mwf
24 interrupt-controller: true
26 '#interrupt-cells':
29 gpio-controller: true
31 '#gpio-cells':
[all …]
/linux/include/linux/platform_data/
H A Demif_plat.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Low power modes - EMIF_PWR_MGMT_CTRL */
23 * EMIF4D - Used in OMAP4
24 * EMIF4D5 - Used in OMAP5
31 * ATTILAPHY - Used in OMAP4
32 * INTELLIPHY - Used in OMAP5
44 * struct ddr_device_info - All information about the DDR device except AC
46 * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc)
49 * @cs1_used: Whether there is a DDR device attached to the second
50 * chip-select(CS1) of this EMIF instance
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
34 cd-gpios:
[all …]
/linux/Documentation/admin-guide/perf/
H A Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
30 - Group 1: PMU Bandwidth Counters. This group has 8 counters that are used
[all …]
H A Dimx-ddr.rst2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for
33 un-supported, and value 1 for supported.
37 --AXI_ID defines AxID matching value.
38 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddcsr.txt21 - compatible
23 Value type: <string>
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
29 Value type: <u32>
33 - #size-cells
35 Value type: <u32>
40 - ranges
42 Value type: <prop-encoded-array>
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
17 /* DDR controller enabled */
30 * Video Frame mapping in DDR
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
145 /* DDR Single Access Page Number */
[all …]
/linux/drivers/devfreq/event/
H A Drockchip-dfi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
8 #include <linux/devfreq-event.h>
67 * struct dmc_count_channel - structure to hold counter values from the DDR controller
69 * @clock_cycles: DDR clock cycles
85 * The dfi controller can monitor DDR load. It has an upper and lower threshold
87 * generated to indicate the DDR frequency should be changed.
118 bool lp5_ckr; /* true if in 4:1 command-to-data clock ratio mode */
126 switch (dfi->ddr_type) { in rockchip_dfi_ddrtype_to_ctrl()
140 ddrmon_ver = readl_relaxed(dfi->regs); in rockchip_dfi_ddrtype_to_ctrl()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "DEVFREQ-Event device Support"
5 The devfreq-event device provide the raw data and events which
6 indicate the current state of devfreq-event device. The provided
7 data from devfreq-event device is used to monitor the state of
11 The devfreq-event device can support the various type of events
23 This add the devfreq-event driver for Exynos SoC. It provides NoC
31 This add the devfreq-event driver for Exynos SoC. It provides PPMU
39 This add the devfreq-event driver for Rockchip SoC. It provides DFI
40 (DDR Monitor Module) driver to count ddr load.
/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 tristate "Arm NI-700 PMU support"
55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
[all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Duncore-cache.json41 …"BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory sta…
51 …"BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
61 …"BriefDescription": "Counts only multi-socket cacheline Directory state updates memory writes issu…
71 …"BriefDescription": "Counts only multi-socket cacheline Directory state updates due to memory writ…
109 …"BriefDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA…
129 …"BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total num…
177 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
243 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
265 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
287 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX8M DDR Controller
10 - Peng Fan <peng.fan@nxp.com>
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
18 switching is implemented by TF-A code which runs from a SRAM area.
27 - enum:
28 - fsl,imx8mn-ddrc
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dpfuze100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robin Gong <yibin.gong@nxp.com>
14 --PFUZE100
16 --PFUZE200
18 --PFUZE3000
20 --PFUZE3001
27 pattern: "^pmic@[0-9]$"
31 - fsl,pfuze100
[all …]
/linux/Documentation/driver-api/memory-devices/
H A Dti-emif.rst1 .. SPDX-License-Identifier: GPL-2.0
32 functions of the driver includes re-configuring AC timing
38 DDR device details and other board dependent and SoC dependent
41 - DDR device details: 'struct ddr_device_info'
42 - Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck'
43 - Custom configurations: customizable policy options through
45 - IP revision
46 - PHY type
53 - freq_pre_notify_handling()
54 - freq_post_notify_handling()
[all …]

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