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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,dcc.yaml4 $id: http://devicetree.org/schemas/soc/qcom/qcom,dcc.yaml#
13 DCC (Data Capture and Compare) is a DMA engine which is used to save
15 or SW trigger. DCC is used to capture and store data for debugging purpose
21 - qcom,sm7150-dcc
22 - qcom,sm8150-dcc
23 - qcom,sc7280-dcc
24 - qcom,sc7180-dcc
25 - qcom,sdm845-dcc
26 - const: qcom,dcc
30 - description: DCC base
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/linux/Documentation/ABI/testing/
H A Ddebugfs-driver-dcc1 What: /sys/kernel/debug/dcc/.../ready
5 This file is used to check the status of the dcc
7 A 'Y' here indicates dcc is ready.
9 What: /sys/kernel/debug/dcc/.../trigger
17 What: /sys/kernel/debug/dcc/.../config_reset
22 a dcc driver to the default configuration. When '1'
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
34 can be one of following dcc instructions: read,
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
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/linux/drivers/tty/hvc/
H A Dhvc_dcc.c14 #include <asm/dcc.h>
19 /* DCC Status Bits */
26 /* Lock to serialize access to DCC fifo */
63 EARLYCON_DECLARE(dcc, dcc_early_console_setup);
93 * Check if the DCC is enabled. If CONFIG_HVC_DCC_SERIALIZE_SMP is enabled,
103 * If we're not on core 0, but we previously confirmed that DCC is in hvc_dcc_check()
129 * Workqueue function that writes the output FIFO to the DCC on core 0.
138 /* While there's data in the output FIFO, write it to the DCC */ in dcc_put_work()
155 * Workqueue function that reads characters from DCC and puts them into the
164 * Read characters from DCC and put them into the input FIFO, as in dcc_get_work()
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H A DKconfig81 bool "ARM JTAG DCC console"
86 This console uses the JTAG DCC on ARM to create a console under the HVC
91 bool "Use DCC only on CPU core 0"
95 Some external debuggers, do not handle reads/writes from/to DCC on more
96 than one CPU core. Each core has its own DCC device registers, so when a
97 CPU core reads or writes from/to DCC, it only accesses its own DCC device.
99 write to the console, it might write to a different DCC.
102 shows the DCC output only from that core's DCC. The result is that
/linux/net/netfilter/
H A Dnf_conntrack_irc.c46 MODULE_DESCRIPTION("IRC (DCC) connection tracking helper");
54 MODULE_PARM_DESC(max_dcc_channels, "max number of expected DCC channels per "
57 MODULE_PARM_DESC(dcc_timeout, "timeout on for unestablished DCC channels");
65 /* tries to get the ip_addr and port out of a dcc command
67 * data pointer to first byte of DCC command data
68 * data_end pointer to last byte of dcc command data
69 * ip returns parsed ip of dcc command
70 * port returns parsed port of dcc command
176 /* strlen(" :\1DCC SENT t AAAAAAAA P\1\n")=26 in help()
187 /* then check that place only for the DCC command */ in help()
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H A Dnf_nat_irc.c25 MODULE_DESCRIPTION("IRC (DCC) NAT helper");
58 /* strlen("\1DCC CHAT chat AAAAAAAA P\1\n")=27 in help()
59 * strlen("\1DCC SCHAT chat AAAAAAAA P\1\n")=28 in help()
60 * strlen("\1DCC SEND F AAAAAAAA P S\1\n")=26 in help()
61 * strlen("\1DCC MOVE F AAAAAAAA P S\1\n")=26 in help()
62 * strlen("\1DCC TSEND F AAAAAAAA P S\1\n")=27 in help()
/linux/Documentation/devicetree/bindings/serial/
H A Darm,dcc.yaml4 $id: http://devicetree.org/schemas/serial/arm,dcc.yaml#
7 title: ARM DCC (Data communication channel) serial emulation
13 ARM DCC (Data communication channel) serial emulation interface available
19 const: arm,dcc
29 compatible = "arm,dcc";
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c170 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); in amdgpu_dm_plane_modifier_has_dcc()
259 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ in amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier()
267 const struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_validate_dcc() argument
278 if (!dcc->enable) in amdgpu_dm_plane_validate_dcc()
304 if (dcc->independent_64b_blks == 0 && in amdgpu_dm_plane_validate_dcc()
317 struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers() argument
332 dcc->enable = 1; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
333 dcc->meta_pitch = afb->base.pitches[1]; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
334 dcc->independent_64b_blks = independent_64b_blks; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
337 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c376 surface->dcc.enable = false; in populate_dml21_dummy_surface_cfg()
377 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_dummy_surface_cfg()
378 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_dummy_surface_cfg()
379 surface->dcc.informative.fraction_of_zero_size_request_plane0 = 0; in populate_dml21_dummy_surface_cfg()
380 surface->dcc.informative.fraction_of_zero_size_request_plane1 = 0; in populate_dml21_dummy_surface_cfg()
442 surface->dcc.enable = plane_state->dcc.enable; in populate_dml21_surface_config_from_plane_state()
443 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_surface_config_from_plane_state()
444 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_surface_config_from_plane_state()
445 …surface->dcc.informative.fraction_of_zero_size_request_plane0 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
446 …surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
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/linux/drivers/bus/
H A Dvexpress-config.c108 u32 *position, u32 *dcc) in vexpress_config_get_topo() argument
116 vexpress_config_find_prop(node, "arm,vexpress,dcc", dcc); in vexpress_config_get_topo()
257 u32 site, position, dcc; in vexpress_syscfg_regmap_init() local
261 &position, &dcc); in vexpress_syscfg_regmap_init()
301 func, site, position, dcc, in vexpress_syscfg_regmap_init()
304 func->template[i] = SYS_CFGCTRL_DCC(dcc); in vexpress_syscfg_regmap_init()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c48 struct dc_plane_dcc_param *dcc, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
H A Ddcn30_hubp.c367 struct dc_plane_dcc_param *dcc) in hubp3_dcc_control_sienna_cichlid() argument
372 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
373 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
374 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c, in hubp3_dcc_control_sienna_cichlid()
375 SECONDARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
376 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
377 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c); in hubp3_dcc_control_sienna_cichlid()
417 struct dc_plane_dcc_param *dcc, in hubp3_program_surface_config() argument
423 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp3_program_surface_config()
425 hubp2_program_size(hubp, format, plane_size, dcc); in hubp3_program_surface_config()
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts144 dcc {
202 temp-dcc {
203 /* DCC internal operating temperature */
206 label = "DCC";
H A Dvexpress-v2p-ca15-tc1.dts141 dcc {
217 temp-dcc {
218 /* DCC internal temperature */
221 label = "DCC";
/linux/arch/arm64/include/asm/
H A Ddcc.h6 * not speculative read the DCC status before executing the read or write
10 * and instead reads the DCC register every time.
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zcu1275-revA.dts22 serial1 = &dcc;
37 &dcc {
H A Dzynqmp-zc1254-revA.dts22 serial1 = &dcc;
37 &dcc {
H A Dzynqmp-zc1232-revA.dts21 serial1 = &dcc;
36 &dcc {
/linux/drivers/irqchip/
H A Dirq-gic-realview.c62 /* new irq mode with no DCC */ in realview_gic_of_init()
69 pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); in realview_gic_of_init()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c167 struct dc_plane_dcc_param *dcc) in hubp1_program_size() argument
180 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
182 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp1_program_size()
185 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
190 if (!dcc->enable) { in hubp1_program_size()
562 struct dc_plane_dcc_param *dcc, in hubp1_program_surface_config() argument
566 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp1_program_surface_config()
568 hubp1_program_size(hubp, format, plane_size, dcc); in hubp1_program_surface_config()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c573 struct dc_plane_dcc_param *dcc) in hubp401_dcc_control() argument
578 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp401_dcc_control()
579 SECONDARY_SURFACE_DCC_EN, dcc->enable); in hubp401_dcc_control()
599 struct dc_plane_dcc_param *dcc) in hubp401_program_size() argument
635 struct dc_plane_dcc_param *dcc, in hubp401_program_surface_config() argument
641 hubp401_dcc_control(hubp, dcc); in hubp401_program_surface_config()
643 hubp401_program_size(hubp, format, plane_size, dcc); in hubp401_program_surface_config()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_ggtt_fencing.c671 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle() local
675 * determined by DCC. For single-channel, neither the CPU in detect_bit_6_swizzle()
682 switch (dcc & DCC_ADDRESSING_MODE_MASK) { in detect_bit_6_swizzle()
689 if (dcc & DCC_CHANNEL_XOR_DISABLE) { in detect_bit_6_swizzle()
696 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { in detect_bit_6_swizzle()
715 if (dcc == 0xffffffff) { in detect_bit_6_swizzle()
/linux/drivers/usb/typec/ucsi/
H A Ducsi_huawei_gaokun.c216 u8 dcc, ddi; in gaokun_ucsi_port_update() local
218 dcc = port_data[offset]; in gaokun_ucsi_port_update()
223 port->ccx = FIELD_GET(GAOKUN_CCX_MASK, dcc); in gaokun_ucsi_port_update()
224 port->mux = FIELD_GET(GAOKUN_MUX_MASK, dcc); in gaokun_ucsi_port_update()
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c320 * this method requires us to always re-calculate watermark when dcc change in pipe_ctx_to_e2e_pipe_params()
323 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
326 * allow us to disable dcc on the fly without re-calculating WM in pipe_ctx_to_e2e_pipe_params()
328 * extra overhead for DCC is quite small. for 1080p WM without in pipe_ctx_to_e2e_pipe_params()
329 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
337 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch; in pipe_ctx_to_e2e_pipe_params()
990 * this method requires us to always re-calculate watermark when dcc change in dcn_validate_bandwidth()
993 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; in dcn_validate_bandwidth()
996 * allow us to disable dcc on the fly without re-calculating WM in dcn_validate_bandwidth()
[all …]
/linux/sound/soc/codecs/
H A Dmt6357.c232 "DCC",
407 /* Audio L/R preamplifier DCC precharge */ in mt6357_set_amic()
423 /* Audio L preamplifier DCC precharge disable */ in mt6357_set_amic()
431 /* Audio R preamplifier DCC precharge disable */ in mt6357_set_amic()
662 /* Audio L preamplifier DCC precharge off */ in mt_pga_left_event()
683 /* disable Audio L preamplifier DCC precharge */ in mt_pga_left_event()
713 /* Audio R preamplifier DCC precharge off */ in mt_pga_right_event()
730 /* disable Audio R preamplifier DCC precharge */ in mt_pga_right_event()
1603 {"Mic Type Mux", "DCC", "ADC"},

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