1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dce_calcs.h"
28 #include "reg_helper.h"
29 #include "basics/conversion.h"
30 #include "dcn401_hubp.h"
31 #include "dal_asic_id.h"
32
33 #define REG(reg)\
34 hubp2->hubp_regs->reg
35
36 #define CTX \
37 hubp2->base.ctx
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
42
hubp401_program_3dlut_fl_addr(struct hubp * hubp,const struct dc_plane_address address)43 static void hubp401_program_3dlut_fl_addr(struct hubp *hubp,
44 const struct dc_plane_address address)
45 {
46 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
47
48 REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part);
49 REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part);
50 }
51
hubp401_program_3dlut_fl_dlg_param(struct hubp * hubp,int refcyc_per_3dlut_group)52 static void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group)
53 {
54 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
55
56 REG_UPDATE(HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, refcyc_per_3dlut_group);
57 }
58
hubp401_enable_3dlut_fl(struct hubp * hubp,bool enable)59 static void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable)
60 {
61 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
62
63 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0);
64 }
65
hubp401_get_3dlut_fl_done(struct hubp * hubp)66 int hubp401_get_3dlut_fl_done(struct hubp *hubp)
67 {
68 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
69 int ret;
70
71 REG_GET(HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, &ret);
72 return ret;
73 }
74
hubp401_program_3dlut_fl_addressing_mode(struct hubp * hubp,enum hubp_3dlut_fl_addressing_mode addr_mode)75 static void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode)
76 {
77 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
78
79 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, addr_mode);
80 }
81
hubp401_program_3dlut_fl_width(struct hubp * hubp,enum hubp_3dlut_fl_width width)82 static void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width)
83 {
84 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
85
86 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width);
87 }
88
hubp401_program_3dlut_fl_tmz_protected(struct hubp * hubp,bool protection_enabled)89 static void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, bool protection_enabled)
90 {
91 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
92
93 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, protection_enabled ? 1 : 0);
94 }
95
hubp401_program_3dlut_fl_crossbar(struct hubp * hubp,enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g,enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r)96 static void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp,
97 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g,
98 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,
99 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r)
100 {
101 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
102
103 REG_UPDATE_3(HUBP_3DLUT_CONTROL,
104 HUBP_3DLUT_CROSSBAR_SELECT_Y_G, bit_slice_y_g,
105 HUBP_3DLUT_CROSSBAR_SELECT_CB_B, bit_slice_cb_b,
106 HUBP_3DLUT_CROSSBAR_SELECT_CR_R, bit_slice_cr_r);
107 }
108
hubp401_update_3dlut_fl_bias_scale(struct hubp * hubp,uint16_t bias,uint16_t scale)109 static void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale)
110 {
111 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
112
113 REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, bias, HUBP0_3DLUT_FL_SCALE, scale);
114 }
115
hubp401_program_3dlut_fl_mode(struct hubp * hubp,enum hubp_3dlut_fl_mode mode)116 static void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode)
117 {
118 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
119
120 REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mode);
121 }
122
hubp401_program_3dlut_fl_format(struct hubp * hubp,enum hubp_3dlut_fl_format format)123 static void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format)
124 {
125 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
126
127 REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format);
128 }
129
hubp401_update_mall_sel(struct hubp * hubp,uint32_t mall_sel,bool c_cursor)130 void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)
131 {
132 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
133
134 // Also cache cursor in MALL if using MALL for SS
135 REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel,
136 USE_MALL_FOR_CURSOR, c_cursor);
137
138 REG_UPDATE_2(DCHUBP_MALL_CONFIG, MALL_PREF_CMD_TYPE, 1, MALL_PREF_MODE, 0);
139 }
140
141
hubp401_init(struct hubp * hubp)142 void hubp401_init(struct hubp *hubp)
143 {
144 //For now nothing to do, HUBPREQ_DEBUG_DB register is removed on DCN4x.
145 }
146
hubp401_vready_at_or_After_vsync(struct hubp * hubp,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)147 void hubp401_vready_at_or_After_vsync(struct hubp *hubp,
148 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
149 {
150 uint32_t value = 0;
151 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
152 /*
153 * if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) <= OTG_V_BLANK_END
154 * Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1
155 * else
156 * Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0
157 */
158 if (pipe_dest->htotal != 0) {
159 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width
160 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
161 value = 1;
162 } else
163 value = 0;
164 }
165
166 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
167 }
168
hubp401_program_requestor(struct hubp * hubp,struct _vcs_dpi_display_rq_regs_st * rq_regs)169 void hubp401_program_requestor(
170 struct hubp *hubp,
171 struct _vcs_dpi_display_rq_regs_st *rq_regs)
172 {
173 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
174
175 REG_UPDATE(HUBPRET_CONTROL,
176 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
177 REG_SET_4(DCN_EXPANSION_MODE, 0,
178 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
179 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
180 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
181 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
182 REG_SET_6(DCHUBP_REQ_SIZE_CONFIG, 0,
183 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
184 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
185 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
186 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
187 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
188 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
189 REG_SET_5(DCHUBP_REQ_SIZE_CONFIG_C, 0,
190 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
191 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
192 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
193 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
194 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
195 }
196
hubp401_program_deadline(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)197 void hubp401_program_deadline(
198 struct hubp *hubp,
199 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
200 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
201 {
202 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
203
204 /* put DLG in mission mode */
205 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
206
207 /* DLG - Per hubp */
208 REG_SET_2(BLANK_OFFSET_0, 0,
209 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
210 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
211
212 REG_SET(BLANK_OFFSET_1, 0,
213 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
214
215 REG_SET(DST_DIMENSIONS, 0,
216 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
217
218 REG_SET_2(DST_AFTER_SCALER, 0,
219 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
220 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
221
222 REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
223 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
224
225 /* DLG - Per luma/chroma */
226 REG_SET(VBLANK_PARAMETERS_1, 0,
227 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
228
229 if (REG(NOM_PARAMETERS_0))
230 REG_SET(NOM_PARAMETERS_0, 0,
231 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
232
233 if (REG(NOM_PARAMETERS_1))
234 REG_SET(NOM_PARAMETERS_1, 0,
235 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
236
237 REG_SET(NOM_PARAMETERS_4, 0,
238 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
239
240 REG_SET(NOM_PARAMETERS_5, 0,
241 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
242
243 REG_SET_2(PER_LINE_DELIVERY, 0,
244 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
245 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
246
247 REG_SET(VBLANK_PARAMETERS_2, 0,
248 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
249
250 if (REG(NOM_PARAMETERS_2))
251 REG_SET(NOM_PARAMETERS_2, 0,
252 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
253
254 if (REG(NOM_PARAMETERS_3))
255 REG_SET(NOM_PARAMETERS_3, 0,
256 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
257
258 REG_SET(NOM_PARAMETERS_6, 0,
259 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
260
261 REG_SET(NOM_PARAMETERS_7, 0,
262 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
263
264 /* TTU - per hubp */
265 REG_SET_2(DCN_TTU_QOS_WM, 0,
266 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
267 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
268
269 /* TTU - per luma/chroma */
270 /* Assumed surf0 is luma and 1 is chroma */
271
272 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
273 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
274 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
275 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
276
277 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
278 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
279 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
280 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
281
282 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
283 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
284 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
285 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
286
287 REG_SET(FLIP_PARAMETERS_1, 0,
288 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
289 REG_SET(HUBP_3DLUT_DLG_PARAM, 0, REFCYC_PER_3DLUT_GROUP, dlg_attr->refcyc_per_tdlut_group);
290
291 REG_UPDATE(DCN_DMDATA_VM_CNTL,
292 REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata);
293 }
294
hubp401_setup(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr,struct _vcs_dpi_display_rq_regs_st * rq_regs,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)295 void hubp401_setup(
296 struct hubp *hubp,
297 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
298 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
299 struct _vcs_dpi_display_rq_regs_st *rq_regs,
300 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
301 {
302 /* otg is locked when this func is called. Register are double buffered.
303 * disable the requestors is not needed
304 */
305 hubp401_vready_at_or_After_vsync(hubp, pipe_dest);
306 hubp401_program_requestor(hubp, rq_regs);
307 hubp401_program_deadline(hubp, dlg_attr, ttu_attr);
308 }
309
hubp401_setup_interdependent(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)310 void hubp401_setup_interdependent(
311 struct hubp *hubp,
312 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
313 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
314 {
315 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
316
317 REG_SET_2(PREFETCH_SETTINGS, 0,
318 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
319 VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
320
321 REG_SET(PREFETCH_SETTINGS_C, 0,
322 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
323
324 REG_SET_2(VBLANK_PARAMETERS_0, 0,
325 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
326 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
327
328 REG_SET_2(FLIP_PARAMETERS_0, 0,
329 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip,
330 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip);
331
332 REG_SET(VBLANK_PARAMETERS_3, 0,
333 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
334
335 REG_SET(VBLANK_PARAMETERS_4, 0,
336 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
337
338 REG_SET(FLIP_PARAMETERS_2, 0,
339 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l);
340
341 REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
342 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
343 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
344
345 REG_SET(DCN_SURF0_TTU_CNTL1, 0,
346 REFCYC_PER_REQ_DELIVERY_PRE,
347 ttu_attr->refcyc_per_req_delivery_pre_l);
348 REG_SET(DCN_SURF1_TTU_CNTL1, 0,
349 REFCYC_PER_REQ_DELIVERY_PRE,
350 ttu_attr->refcyc_per_req_delivery_pre_c);
351 REG_SET(DCN_CUR0_TTU_CNTL1, 0,
352 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
353
354 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
355 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
356 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
357 }
358
359
hubp401_program_surface_flip_and_addr(struct hubp * hubp,const struct dc_plane_address * address,bool flip_immediate)360 bool hubp401_program_surface_flip_and_addr(
361 struct hubp *hubp,
362 const struct dc_plane_address *address,
363 bool flip_immediate)
364 {
365 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
366
367 //program flip type
368 REG_UPDATE(DCSURF_FLIP_CONTROL,
369 SURFACE_FLIP_TYPE, flip_immediate);
370
371 // Program VMID reg
372 if (flip_immediate == 0)
373 REG_UPDATE(VMID_SETTINGS_0,
374 VMID, address->vmid);
375
376 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
377 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);
378 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
379
380 } else {
381 // turn off stereo if not in stereo
382 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
383 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
384 }
385
386 /* HW automatically latch rest of address register on write to
387 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
388 *
389 * program high first and then the low addr, order matters!
390 */
391 switch (address->type) {
392 case PLN_ADDR_TYPE_GRAPHICS:
393 if (address->grph.addr.quad_part == 0)
394 break;
395
396 REG_UPDATE(DCSURF_SURFACE_CONTROL,
397 PRIMARY_SURFACE_TMZ, address->tmz_surface);
398
399 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
400 PRIMARY_SURFACE_ADDRESS_HIGH,
401 address->grph.addr.high_part);
402
403 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
404 PRIMARY_SURFACE_ADDRESS,
405 address->grph.addr.low_part);
406 break;
407 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
408 if (address->video_progressive.luma_addr.quad_part == 0
409 || address->video_progressive.chroma_addr.quad_part == 0)
410 break;
411
412 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
413 PRIMARY_SURFACE_TMZ, address->tmz_surface,
414 PRIMARY_SURFACE_TMZ_C, address->tmz_surface);
415
416 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
417 PRIMARY_SURFACE_ADDRESS_HIGH_C,
418 address->video_progressive.chroma_addr.high_part);
419
420 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
421 PRIMARY_SURFACE_ADDRESS_C,
422 address->video_progressive.chroma_addr.low_part);
423
424 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
425 PRIMARY_SURFACE_ADDRESS_HIGH,
426 address->video_progressive.luma_addr.high_part);
427
428 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
429 PRIMARY_SURFACE_ADDRESS,
430 address->video_progressive.luma_addr.low_part);
431 break;
432 case PLN_ADDR_TYPE_GRPH_STEREO:
433 if (address->grph_stereo.left_addr.quad_part == 0)
434 break;
435 if (address->grph_stereo.right_addr.quad_part == 0)
436 break;
437
438 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
439 PRIMARY_SURFACE_TMZ, address->tmz_surface,
440 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
441 SECONDARY_SURFACE_TMZ, address->tmz_surface,
442 SECONDARY_SURFACE_TMZ_C, address->tmz_surface);
443
444 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,
445 SECONDARY_SURFACE_ADDRESS_HIGH_C,
446 address->grph_stereo.right_alpha_addr.high_part);
447
448 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,
449 SECONDARY_SURFACE_ADDRESS_C,
450 address->grph_stereo.right_alpha_addr.low_part);
451
452 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
453 SECONDARY_SURFACE_ADDRESS_HIGH,
454 address->grph_stereo.right_addr.high_part);
455
456 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
457 SECONDARY_SURFACE_ADDRESS,
458 address->grph_stereo.right_addr.low_part);
459
460 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
461 PRIMARY_SURFACE_ADDRESS_HIGH_C,
462 address->grph_stereo.left_alpha_addr.high_part);
463
464 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
465 PRIMARY_SURFACE_ADDRESS_C,
466 address->grph_stereo.left_alpha_addr.low_part);
467
468 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
469 PRIMARY_SURFACE_ADDRESS_HIGH,
470 address->grph_stereo.left_addr.high_part);
471
472 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
473 PRIMARY_SURFACE_ADDRESS,
474 address->grph_stereo.left_addr.low_part);
475 break;
476 case PLN_ADDR_TYPE_RGBEA:
477 if (address->rgbea.addr.quad_part == 0
478 || address->rgbea.alpha_addr.quad_part == 0)
479 break;
480
481 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
482 PRIMARY_SURFACE_TMZ, address->tmz_surface,
483 PRIMARY_SURFACE_TMZ_C, address->tmz_surface);
484
485 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
486 PRIMARY_SURFACE_ADDRESS_HIGH_C,
487 address->rgbea.alpha_addr.high_part);
488
489 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
490 PRIMARY_SURFACE_ADDRESS_C,
491 address->rgbea.alpha_addr.low_part);
492
493 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
494 PRIMARY_SURFACE_ADDRESS_HIGH,
495 address->rgbea.addr.high_part);
496
497 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
498 PRIMARY_SURFACE_ADDRESS,
499 address->rgbea.addr.low_part);
500 break;
501 default:
502 BREAK_TO_DEBUGGER();
503 break;
504 }
505
506 hubp->request_address = *address;
507
508 return true;
509 }
510
hubp401_dcc_control(struct hubp * hubp,struct dc_plane_dcc_param * dcc)511 void hubp401_dcc_control(struct hubp *hubp,
512 struct dc_plane_dcc_param *dcc)
513 {
514 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
515
516 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
517 PRIMARY_SURFACE_DCC_EN, dcc->enable,
518 SECONDARY_SURFACE_DCC_EN, dcc->enable);
519 }
520
hubp401_program_tiling(struct dcn20_hubp * hubp2,const union dc_tiling_info * info,const enum surface_pixel_format pixel_format)521 void hubp401_program_tiling(
522 struct dcn20_hubp *hubp2,
523 const union dc_tiling_info *info,
524 const enum surface_pixel_format pixel_format)
525 {
526 /* DCSURF_ADDR_CONFIG still shows up in reg spec, but does not need to be programmed for DCN4x
527 * All 4 fields NUM_PIPES, PIPE_INTERLEAVE, MAX_COMPRESSED_FRAGS and NUM_PKRS are irrelevant.
528 *
529 * DIM_TYPE field in DCSURF_TILING for Display is always 1 (2D dimension) which is HW default.
530 */
531 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle);
532 }
533
hubp401_program_size(struct hubp * hubp,enum surface_pixel_format format,const struct plane_size * plane_size,struct dc_plane_dcc_param * dcc)534 void hubp401_program_size(
535 struct hubp *hubp,
536 enum surface_pixel_format format,
537 const struct plane_size *plane_size,
538 struct dc_plane_dcc_param *dcc)
539 {
540 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
541 uint32_t pitch, pitch_c;
542 bool use_pitch_c = false;
543
544 /* Program data pitch (calculation from addrlib)
545 * 444 or 420 luma
546 */
547 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
548 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
549 use_pitch_c = use_pitch_c
550 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
551 if (use_pitch_c) {
552 ASSERT(plane_size->chroma_pitch != 0);
553 /* Chroma pitch zero can cause system hang! */
554
555 pitch = plane_size->surface_pitch - 1;
556 pitch_c = plane_size->chroma_pitch - 1;
557 } else {
558 pitch = plane_size->surface_pitch - 1;
559 pitch_c = 0;
560 }
561
562 REG_UPDATE(DCSURF_SURFACE_PITCH, PITCH, pitch);
563
564 if (use_pitch_c)
565 REG_UPDATE(DCSURF_SURFACE_PITCH_C, PITCH_C, pitch_c);
566 }
567
hubp401_program_surface_config(struct hubp * hubp,enum surface_pixel_format format,union dc_tiling_info * tiling_info,struct plane_size * plane_size,enum dc_rotation_angle rotation,struct dc_plane_dcc_param * dcc,bool horizontal_mirror,unsigned int compat_level)568 void hubp401_program_surface_config(
569 struct hubp *hubp,
570 enum surface_pixel_format format,
571 union dc_tiling_info *tiling_info,
572 struct plane_size *plane_size,
573 enum dc_rotation_angle rotation,
574 struct dc_plane_dcc_param *dcc,
575 bool horizontal_mirror,
576 unsigned int compat_level)
577 {
578 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
579
580 hubp401_dcc_control(hubp, dcc);
581 hubp401_program_tiling(hubp2, tiling_info, format);
582 hubp401_program_size(hubp, format, plane_size, dcc);
583 hubp2_program_rotation(hubp, rotation, horizontal_mirror);
584 hubp2_program_pixel_format(hubp, format);
585 }
586
hubp401_set_viewport(struct hubp * hubp,const struct rect * viewport,const struct rect * viewport_c)587 void hubp401_set_viewport(
588 struct hubp *hubp,
589 const struct rect *viewport,
590 const struct rect *viewport_c)
591 {
592 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
593
594 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
595 PRI_VIEWPORT_WIDTH, viewport->width,
596 PRI_VIEWPORT_HEIGHT, viewport->height);
597
598 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
599 PRI_VIEWPORT_X_START, viewport->x,
600 PRI_VIEWPORT_Y_START, viewport->y);
601
602 /*for stereo*/
603 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
604 SEC_VIEWPORT_WIDTH, viewport->width,
605 SEC_VIEWPORT_HEIGHT, viewport->height);
606
607 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
608 SEC_VIEWPORT_X_START, viewport->x,
609 SEC_VIEWPORT_Y_START, viewport->y);
610
611 /* DC supports NV12 only at the moment */
612 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
613 PRI_VIEWPORT_WIDTH_C, viewport_c->width,
614 PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
615
616 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
617 PRI_VIEWPORT_X_START_C, viewport_c->x,
618 PRI_VIEWPORT_Y_START_C, viewport_c->y);
619
620 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
621 SEC_VIEWPORT_WIDTH_C, viewport_c->width,
622 SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
623
624 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
625 SEC_VIEWPORT_X_START_C, viewport_c->x,
626 SEC_VIEWPORT_Y_START_C, viewport_c->y);
627 }
628
hubp401_program_mcache_id_and_split_coordinate(struct hubp * hubp,struct dml2_hubp_pipe_mcache_regs * mcache_regs)629 void hubp401_program_mcache_id_and_split_coordinate(
630 struct hubp *hubp,
631 struct dml2_hubp_pipe_mcache_regs *mcache_regs)
632 {
633 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
634
635 REG_SET_8(DCHUBP_MCACHEID_CONFIG, 0,
636 MCACHEID_REG_READ_1H_P0, mcache_regs->main.p0.mcache_id_first,
637 MCACHEID_REG_READ_2H_P0, mcache_regs->main.p0.mcache_id_second,
638 MCACHEID_REG_READ_1H_P1, mcache_regs->main.p1.mcache_id_first,
639 MCACHEID_REG_READ_2H_P1, mcache_regs->main.p1.mcache_id_second,
640 MCACHEID_MALL_PREF_1H_P0, mcache_regs->mall.p0.mcache_id_first,
641 MCACHEID_MALL_PREF_2H_P0, mcache_regs->mall.p0.mcache_id_second,
642 MCACHEID_MALL_PREF_1H_P1, mcache_regs->mall.p1.mcache_id_first,
643 MCACHEID_MALL_PREF_2H_P1, mcache_regs->mall.p1.mcache_id_second);
644
645 REG_SET_2(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, 0,
646 VIEWPORT_MCACHE_SPLIT_COORDINATE, mcache_regs->main.p0.split_location,
647 VIEWPORT_MCACHE_SPLIT_COORDINATE_C, mcache_regs->main.p1.split_location);
648 }
hubp401_set_flip_int(struct hubp * hubp)649 void hubp401_set_flip_int(struct hubp *hubp)
650 {
651 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
652
653 REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT,
654 SURFACE_FLIP_INT_MASK, 1);
655
656 return;
657 }
658
hubp401_in_blank(struct hubp * hubp)659 bool hubp401_in_blank(struct hubp *hubp)
660 {
661 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
662 uint32_t in_blank;
663
664 REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank);
665 return in_blank ? true : false;
666 }
667
668
hubp401_cursor_set_position(struct hubp * hubp,const struct dc_cursor_position * pos,const struct dc_cursor_mi_param * param)669 void hubp401_cursor_set_position(
670 struct hubp *hubp,
671 const struct dc_cursor_position *pos,
672 const struct dc_cursor_mi_param *param)
673 {
674 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
675 int x_pos = pos->x - param->recout.x;
676 int y_pos = pos->y - param->recout.y;
677 int rec_x_offset = x_pos - pos->x_hotspot;
678 int rec_y_offset = y_pos - pos->y_hotspot;
679 int dst_x_offset;
680 int x_pos_viewport = 0;
681 int x_hot_viewport = 0;
682 uint32_t cur_en = pos->enable ? 1 : 0;
683
684 hubp->curs_pos = *pos;
685
686 /* Recout is zero for pipes if the entire dst_rect is contained
687 * within preceeding ODM slices.
688 */
689 if (param->recout.width) {
690 x_pos_viewport = x_pos * param->viewport.width / param->recout.width;
691 x_hot_viewport = pos->x_hotspot * param->viewport.width / param->recout.width;
692 } else {
693 ASSERT(!cur_en || x_pos == 0);
694 ASSERT(!cur_en || pos->x_hotspot == 0);
695 }
696
697 /*
698 * Guard aganst cursor_set_position() from being called with invalid
699 * attributes
700 */
701 if (hubp->curs_attr.address.quad_part == 0)
702 return;
703
704 /* Translate the x position of the cursor from rect
705 * space into viewport space. CURSOR_DST_X_OFFSET
706 * is the offset relative to viewport start position.
707 */
708 dst_x_offset = x_pos_viewport - x_hot_viewport *
709 (1 + hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION);
710 dst_x_offset = (dst_x_offset >= 0) ? dst_x_offset : 0;
711 dst_x_offset *= param->ref_clk_khz;
712 dst_x_offset /= param->pixel_clk_khz;
713
714 ASSERT(param->h_scale_ratio.value);
715
716 if (param->h_scale_ratio.value)
717 dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
718 dc_fixpt_from_int(dst_x_offset),
719 param->h_scale_ratio));
720
721 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
722 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
723
724 REG_UPDATE(CURSOR_CONTROL,
725 CURSOR_ENABLE, cur_en);
726
727 REG_SET_2(CURSOR_POSITION, 0,
728 CURSOR_X_POSITION, x_pos,
729 CURSOR_Y_POSITION, y_pos);
730
731 REG_SET_2(CURSOR_HOT_SPOT, 0,
732 CURSOR_HOT_SPOT_X, pos->x_hotspot,
733 CURSOR_HOT_SPOT_Y, pos->y_hotspot);
734
735 REG_SET(CURSOR_DST_OFFSET, 0,
736 CURSOR_DST_X_OFFSET, dst_x_offset);
737
738 /* Cursor Position Register Config */
739 hubp->pos.cur_ctl.bits.cur_enable = cur_en;
740 hubp->pos.position.bits.x_pos = pos->x;
741 hubp->pos.position.bits.y_pos = pos->y;
742 hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;
743 hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;
744 hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;
745 /* Cursor Rectangle Cache
746 * Cursor bitmaps have different hotspot values
747 * There's a possibility that the above logic returns a negative value,
748 * so we clamp them to 0
749 */
750 if (rec_x_offset < 0)
751 rec_x_offset = 0;
752 if (rec_y_offset < 0)
753 rec_y_offset = 0;
754 /* Save necessary cursor info x, y position. w, h is saved in attribute func. */
755 hubp->cur_rect.x = rec_x_offset + param->recout.x;
756 hubp->cur_rect.y = rec_y_offset + param->recout.y;
757 }
758
hubp401_read_state(struct hubp * hubp)759 void hubp401_read_state(struct hubp *hubp)
760 {
761 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
762 struct dcn_hubp_state *s = &hubp2->state;
763 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
764 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
765 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
766
767 /* Requester */
768 REG_GET(HUBPRET_CONTROL,
769 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
770 REG_GET_4(DCN_EXPANSION_MODE,
771 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
772 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
773 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
774 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
775
776 REG_GET_5(DCHUBP_REQ_SIZE_CONFIG,
777 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
778 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
779 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
780 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
781 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
782
783 REG_GET_5(DCHUBP_REQ_SIZE_CONFIG_C,
784 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
785 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
786 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
787 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
788 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
789
790 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,
791 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr);
792
793 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,
794 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr);
795
796 /* DLG - Per hubp */
797 REG_GET_2(BLANK_OFFSET_0,
798 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
799 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
800
801 REG_GET(BLANK_OFFSET_1,
802 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
803
804 REG_GET(DST_DIMENSIONS,
805 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
806
807 REG_GET_2(DST_AFTER_SCALER,
808 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
809 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
810
811 REG_GET_2(PREFETCH_SETTINGS,
812 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
813 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
814
815 REG_GET_2(VBLANK_PARAMETERS_0,
816 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
817 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
818
819 REG_GET(REF_FREQ_TO_PIX_FREQ,
820 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
821
822 /* DLG - Per luma/chroma */
823 REG_GET(VBLANK_PARAMETERS_1,
824 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
825
826 REG_GET(VBLANK_PARAMETERS_3,
827 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
828
829 REG_GET(NOM_PARAMETERS_0,
830 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
831
832 REG_GET(NOM_PARAMETERS_1,
833 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
834
835 REG_GET(NOM_PARAMETERS_4,
836 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
837
838 REG_GET(NOM_PARAMETERS_5,
839 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
840
841 REG_GET_2(PER_LINE_DELIVERY_PRE,
842 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
843 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
844
845 REG_GET_2(PER_LINE_DELIVERY,
846 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
847 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
848
849 REG_GET(PREFETCH_SETTINGS_C,
850 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
851
852 REG_GET(VBLANK_PARAMETERS_2,
853 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
854
855 REG_GET(VBLANK_PARAMETERS_4,
856 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
857
858 REG_GET(NOM_PARAMETERS_2,
859 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
860
861 REG_GET(NOM_PARAMETERS_3,
862 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
863
864 REG_GET(NOM_PARAMETERS_6,
865 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
866
867 REG_GET(NOM_PARAMETERS_7,
868 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
869
870 /* TTU - per hubp */
871 REG_GET_2(DCN_TTU_QOS_WM,
872 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
873 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
874
875 REG_GET_2(DCN_GLOBAL_TTU_CNTL,
876 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
877 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
878
879 /* TTU - per luma/chroma */
880 /* Assumed surf0 is luma and 1 is chroma */
881
882 REG_GET_3(DCN_SURF0_TTU_CNTL0,
883 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
884 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
885 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
886
887 REG_GET(DCN_SURF0_TTU_CNTL1,
888 REFCYC_PER_REQ_DELIVERY_PRE,
889 &ttu_attr->refcyc_per_req_delivery_pre_l);
890
891 REG_GET_3(DCN_SURF1_TTU_CNTL0,
892 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
893 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
894 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
895
896 REG_GET(DCN_SURF1_TTU_CNTL1,
897 REFCYC_PER_REQ_DELIVERY_PRE,
898 &ttu_attr->refcyc_per_req_delivery_pre_c);
899
900 /* Rest of hubp */
901 REG_GET(DCSURF_SURFACE_CONFIG,
902 SURFACE_PIXEL_FORMAT, &s->pixel_format);
903
904 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
905 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
906
907 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
908 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
909
910 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
911 PRI_VIEWPORT_WIDTH, &s->viewport_width,
912 PRI_VIEWPORT_HEIGHT, &s->viewport_height);
913
914 REG_GET_2(DCSURF_SURFACE_CONFIG,
915 ROTATION_ANGLE, &s->rotation_angle,
916 H_MIRROR_EN, &s->h_mirror_en);
917
918 REG_GET(DCSURF_TILING_CONFIG,
919 SW_MODE, &s->sw_mode);
920
921 REG_GET(DCSURF_SURFACE_CONTROL,
922 PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
923
924 REG_GET_3(DCHUBP_CNTL,
925 HUBP_BLANK_EN, &s->blank_en,
926 HUBP_TTU_DISABLE, &s->ttu_disable,
927 HUBP_UNDERFLOW_STATUS, &s->underflow_status);
928
929 REG_GET(HUBP_CLK_CNTL,
930 HUBP_CLOCK_ENABLE, &s->clock_en);
931
932 REG_GET(DCN_GLOBAL_TTU_CNTL,
933 MIN_TTU_VBLANK, &s->min_ttu_vblank);
934
935 REG_GET_2(DCN_TTU_QOS_WM,
936 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
937 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
938
939 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
940 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
941
942 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
943 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
944
945 s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);
946
947 s->hubp_cntl = REG_READ(DCHUBP_CNTL);
948 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
949 }
950
hubp401_set_unbounded_requesting(struct hubp * hubp,bool enable)951 void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable)
952 {
953 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
954
955 REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable);
956
957 /* To ensure that cursor fetching starts as early as possible in
958 * the display prefetch, set CURSOR_REQ_MODE = 1 always.
959 * The setting of CURSOR_REQ_MODE = 0 is no longer supported in
960 * DCN4x as a fall back to legacy behavior of fetching cursor
961 * just before it appears on the screen.
962 */
963 REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, 1);
964 }
965
966 static struct hubp_funcs dcn401_hubp_funcs = {
967 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
968 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
969 .hubp_program_surface_flip_and_addr = hubp401_program_surface_flip_and_addr,
970 .hubp_program_surface_config = hubp401_program_surface_config,
971 .hubp_is_flip_pending = hubp2_is_flip_pending,
972 .hubp_setup = hubp401_setup,
973 .hubp_setup_interdependent = hubp401_setup_interdependent,
974 .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
975 .set_blank = hubp2_set_blank,
976 .set_blank_regs = hubp2_set_blank_regs,
977 .mem_program_viewport = hubp401_set_viewport,
978 .set_cursor_attributes = hubp32_cursor_set_attributes,
979 .set_cursor_position = hubp401_cursor_set_position,
980 .hubp_clk_cntl = hubp2_clk_cntl,
981 .hubp_vtg_sel = hubp2_vtg_sel,
982 .dmdata_set_attributes = hubp3_dmdata_set_attributes,
983 .dmdata_load = hubp2_dmdata_load,
984 .dmdata_status_done = hubp2_dmdata_status_done,
985 .hubp_read_state = hubp401_read_state,
986 .hubp_clear_underflow = hubp2_clear_underflow,
987 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
988 .hubp_init = hubp401_init,
989 .set_unbounded_requesting = hubp401_set_unbounded_requesting,
990 .hubp_soft_reset = hubp31_soft_reset,
991 .hubp_set_flip_int = hubp401_set_flip_int,
992 .hubp_in_blank = hubp401_in_blank,
993 .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,
994 .hubp_update_mall_sel = hubp401_update_mall_sel,
995 .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,
996 .hubp_program_mcache_id_and_split_coordinate = hubp401_program_mcache_id_and_split_coordinate,
997 .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale,
998 .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode,
999 .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format,
1000 .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr,
1001 .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param,
1002 .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl,
1003 .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode,
1004 .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width,
1005 .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected,
1006 .hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar,
1007 .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done
1008 };
1009
hubp401_construct(struct dcn20_hubp * hubp2,struct dc_context * ctx,uint32_t inst,const struct dcn_hubp2_registers * hubp_regs,const struct dcn_hubp2_shift * hubp_shift,const struct dcn_hubp2_mask * hubp_mask)1010 bool hubp401_construct(
1011 struct dcn20_hubp *hubp2,
1012 struct dc_context *ctx,
1013 uint32_t inst,
1014 const struct dcn_hubp2_registers *hubp_regs,
1015 const struct dcn_hubp2_shift *hubp_shift,
1016 const struct dcn_hubp2_mask *hubp_mask)
1017 {
1018 hubp2->base.funcs = &dcn401_hubp_funcs;
1019 hubp2->base.ctx = ctx;
1020 hubp2->hubp_regs = hubp_regs;
1021 hubp2->hubp_shift = hubp_shift;
1022 hubp2->hubp_mask = hubp_mask;
1023 hubp2->base.inst = inst;
1024 hubp2->base.opp_id = OPP_ID_INVALID;
1025 hubp2->base.mpcc_id = 0xf;
1026
1027 return true;
1028 }
1029