Home
last modified time | relevance | path

Searched +full:cortex +full:- +full:a8 (Results 1 – 24 of 24) sorted by relevance

/linux/Documentation/devicetree/bindings/arm/
H A Darm,realview.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
31 - const: arm,realview-pb1176
[all …]
/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
[all …]
/linux/arch/arm/boot/dts/arm/
H A Darm-realview-pba8.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
27 model = "ARM RealView Platform Baseboard for Cortex-A8";
28 compatible = "arm,realview-pba8";
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "arm,realview-smp";
38 compatible = "arm,cortex-a8";
44 compatible = "arm,cortex-a8-pmu";
45 interrupt-parent = <&intc>;
[all …]
/linux/arch/arm/mm/
H A Dproc-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
15 #include <asm/asm-offsets.h>
17 #include <asm/pgtable-hwdef.h>
20 #include "proc-macros.S"
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 .arch armv7-a
49 * - loc - location to jump to for soft reset
[all …]
H A Dproc-v7-2level.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mm/proc-v7-2level.S
27 .arch armv7-a
34 * - pgd_phys - physical address of new TTB
37 * - we are not using split page tables
40 * even on Cortex-A8 revisions not affected by 430973.
45 mmid r1, r1 @ get mm->context.id
69 * - ptep - pointer to level 2 translation table entry
71 * - pte - PTE value to store
72 * - ext - value for extended PTE bits
[all …]
/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
173 relocations. The combined range is -/+ 256 MiB, which is usually
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
[all …]
/linux/Documentation/arch/arm/
H A Dsunxi.rst10 ------------
11 Linux kernel mach directory: arch/arm/mach-sunxi
16 - Allwinner F20 (sun3i)
20 * ARM Cortex-A8 based SoCs
21 - Allwinner A10 (sun4i)
25 http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
28 …http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf
30 - Allwinner A10s (sun5i)
34 http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
36 - Allwinner A13 / R8 (sun5i)
[all …]
/linux/arch/arm/mach-imx/
H A Dcpu-imx5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
19 static int mx5_cpu_rev = -1;
43 u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); in get_mx51_srev()
61 if (mx5_cpu_rev == -1) in mx51_revision()
72 * Dependent on link order - so the assumption is that vfp_init is called
89 u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); in get_mx53_srev()
109 if (mx5_cpu_rev == -1) in mx53_revision()
135 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); in imx5_pmu_init()
139 if (!of_property_read_bool(np, "secure-reg-access")) in imx5_pmu_init()
[all …]
/linux/lib/crypto/arm/
H A Dsha512-armv4.pl2 # SPDX-License-Identifier: GPL-2.0
22 # by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
27 # Rescheduling for dual-issue pipeline resulted in 6% improvement on
28 # Cortex A8 core and ~40 cycles per processed byte.
32 # Profiler-assisted and platform-specific optimization resulted in 7%
33 # improvement on Coxtex A8 core and ~38 cycles per byte.
37 # Add NEON implementation. On Cortex A8 it was measured to process
38 # one byte in 23.3 cycles or ~60% faster than integer-only code.
44 # Technical writers asserted that 3-way S4 pipeline can sustain
46 # not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
[all …]
H A Dsha1-armv4-large.S2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
42 @ i-cache availability, branch penalties, etc.
49 @ [***] which is also ~35% better than compiler generated code. Dual-
50 @ issue Cortex A8 core was measured to process input block in
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
56 @ Cortex A8 core and in absolute terms ~870 cycles per input block
[all …]
H A Dsha256-armv4.pl2 # SPDX-License-Identifier: GPL-2.0
21 # Performance is ~2x better than gcc 3.4 generated code and in "abso-
22 # lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
23 # byte [on single-issue Xscale PXA250 core].
27 # Rescheduling for dual-issue pipeline resulted in 22% improvement on
28 # Cortex A8 core and ~20 cycles per processed byte.
32 # Profiler-assisted and platform-specific optimization resulted in 16%
33 # improvement on Cortex A8 core and ~15.4 cycles per processed byte.
37 # Add NEON implementation. On Cortex A8 it was measured to process one
38 # byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
[all …]
H A Dpoly1305-armv4.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, initially for the OpenSSL
9 # IALU(*)/gcc-4.4 NEON
11 # ARM11xx(ARMv6) 7.78/+100% -
12 # Cortex-A5 6.35/+130% 3.00
13 # Cortex-A8 6.25/+115% 2.36
14 # Cortex-A9 5.10/+95% 2.55
15 # Cortex-A15 3.85/+85% 1.25(**)
18 # (*) this is for -march=armv6, i.e. with bunch of ldrb loading data;
19 # (**) these are trade-off results, they can be improved by ~8% but at
[all …]
/linux/arch/arm/boot/dts/cnxt/
H A Dcx92755.dtsi8 * This file is dual-licensed: you can use it either under the terms
48 #address-cells = <1>;
49 #size-cells = <1>;
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a8";
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <200000000>;
[all …]
/linux/arch/arm/mach-omap2/
H A Dsleep33xx.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2012-2018 Texas Instruments Incorporated - https://www.ti.com/
11 #include <linux/ti-emif-sram.h>
17 #include "pm-asm-offsets.h"
27 .arch armv7-a
31 stmfd sp!, {r4 - r11, lr} @ save registers on stack
140 * NOPs as per Cortex-A8 pipeline.
165 /* Re-enable EMIF */
197 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
202 .word . - am33xx_do_wfi
[all …]
H A Did.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap2/id.c
10 * Copyright (C) 2009-11 Texas Instruments
11 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
86 /*----------------------------------------------------------------------------*/
123 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); in omap_get_die_id()
124 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); in omap_get_die_id()
125 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); in omap_get_die_id()
126 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); in omap_get_die_id()
130 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); in omap_get_die_id()
[all …]
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include "imx51-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
42 tzic: tz-interrupt-controller@e0000000 {
[all …]
H A Dimx53.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include "imx53-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
[all …]
H A Dimx50.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include "imx50-pinfunc.h"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/imx5-clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
47 #address-cells = <1>;
48 #size-cells = <0>;
51 compatible = "arm,cortex-a8";
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/omap.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
33 #address-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
19 #include <dt-bindings/clock/s5pv210.h>
20 #include <dt-bindings/clock/s5pv210-audss.h>
23 #address-cells = <1>;
24 #size-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a8";
55 xxti: oscillator-0 {
[all …]