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/linux/arch/mips/boot/dts/loongson/
H A Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
17 cpu0: cpu@0 {
18 device_type = "cpu";
21 #clock-cells = <1>;
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/linux/Documentation/dev-tools/
H A Dcheckuapi.rst1 .. SPDX-License-Identifier: GPL-2.0-only
7 The UAPI checker (``scripts/check-uapi.sh``) is a shell script which
8 checks UAPI header files for userspace backwards-compatibility across
14 This section will describe the options with which ``check-uapi.sh``
19 check-uapi.sh [-b BASE_REF] [-p PAST_REF] [-j N] [-l ERROR_LOG] [-i] [-q] [-v]
23 -b BASE_REF Base git reference to use for comparison. If unspecified or empty,
26 -p PAST_REF Compare BASE_REF to PAST_REF (e.g. -p v6.1). If unspecified or empty,
29 -j JOBS Number of checks to run in parallel (default: number of CPU cores).
30 -l ERROR_LOG Write error log to file (default: no error log is generated).
31 -i Ignore ambiguous changes that may or may not break UAPI compatibility.
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/linux/Documentation/filesystems/nfs/
H A Dknfsd-stats.rst5 :Authors: Greg Banks <gnb@sgi.com> - 26 Mar 2009
13 program from the nfs-utils distribution provides a helpful command-line
48 packets-arrived
58 However this is a more accurate and less workload-dependent measure
59 of how much CPU load is being placed on the sunrpc server layer
62 sockets-enqueued
68 network-facing work to be done but it couldn't be done immediately,
70 rate of change for this counter is zero; significantly non-zero
74 pool for the NFS workload (the workload is thread-limited), in which
78 threads-woken
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/linux/drivers/net/dsa/
H A Dvitesse-vsc73xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * a sixth CPU port facing the processor with an RGMII interface. These ports
11 * The VSC7398 has 8 ports, port 7 is again the CPU port.
18 * struct vsc73xx_portinfo - port data structure: contains storage data
34 * struct vsc73xx - VSC73xx state container: main data structure
42 * @ops: Structure with hardware-dependent operations
65 * struct vsc73xx_ops - VSC73xx methods container
66 * @read: Method for register reading over the hardware-dependent interface
67 * @write: Method for register writing over the hardware-dependent interface
77 * struct vsc73xx_bridge_vlan - VSC73xx driver structure which keeps vlan
H A Dvitesse-vsc73xx-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
8 * These switches have a built-in 8051 CPU and can download and execute a
9 * firmware in this CPU. They can also be configured to use an external CPU
10 * handling the switch in a memory-mapped manner by connecting to that external
11 * CPU's memory bus.
34 #include "vitesse-vsc73xx.h"
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H A Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
49 if (priv->bus) in mt7530_mutex_lock()
50 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
56 if (priv->bus) in mt7530_mutex_unlock()
57 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
63 struct mii_bus *bus = priv->bus; in core_write()
69 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
75 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
81 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
87 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmicrel,ks8995.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 the early-to-mid 2000s. The chip features a CPU port and four outgoing ports,
19 fabric, connected to an external MII interface name MII-P5. This is
20 unrelated from the CPU-facing port 5 which is used for DSA MII traffic.
25 - micrel,ks8995
26 - micrel,ksz8795
27 - micrel,ksz8864
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/linux/include/uapi/linux/
H A Ddevlink.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * include/uapi/linux/devlink.h - Network physical device Netlink interface
146 DEVLINK_CMD_MAX = __DEVLINK_CMD_MAX - 1
161 /* static threshold - limiting the maximum number of bytes.
162 * dynamic threshold - limiting the maximum number of bytes
167 * While Free_Buffer is the amount of none-occupie
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/linux/Documentation/networking/dsa/
H A Ddsa.rst22 An Ethernet switch typically comprises multiple front-panel ports and one
23 or more CPU or management ports. The DSA subsystem currently relies on the
27 gateways, or even top-of-rack switches. This host Ethernet controller will
28 be later referred to as "conduit" and "cpu" in DSA terminology and code.
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
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H A Dconfiguration.rst1 .. SPDX-License-Identifier: GPL-2.0
10 .. _dsa-config-showcases:
13 -----------------------
33 interface. The CPU port is the switch port connected to an Ethernet MAC chip.
42 - when a DSA user interface is brought up, the conduit interface is
44 - when the conduit interface is brought down, all DSA user interfaces are
71 * lan1: 192.0.2.1/30 (192.0.2.0 - 192.0.2.3)
72 * lan2: 192.0.2.5/30 (192.0.2.4 - 192.0.2.7)
73 * lan3: 192.0.2.9/30 (192.0.2.8 - 192.0.2.11)
76 * br0: 192.0.2.129/25 (192.0.2.128 - 192.0.2.255)
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/linux/include/net/page_pool/
H A Dtypes.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <linux/dma-direction.h>
17 * DMA-synced-for-device according to
20 * Please note DMA-sync-for-CPU is still
38 #define PP_DMA_INDEX_LIMIT XA_LIMIT(1, BIT(PP_DMA_INDEX_BITS) - 1)
44 * use-case. The NAPI budget is 64 packets. After a NAPI poll the RX
48 * Keeping room for more objects, is due to XDP_DROP use-case. As
62 * struct page_pool_params - page pool parameters
67 * @dev: device, for DMA pre-mapping purposes
101 * struct page_pool_alloc_stats - allocation statistics
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H A Dhelpers.h1 /* SPDX-License-Identifier: GPL-2.0
32 * 'struct page' and atomic operation for page->pp_ref_count.
34 * The API keeps track of in-flight pages, in order to let API users know when
37 * attach the page_pool object to a page_pool-aware object like skbs marked with
42 * recycle the page, or in case of page->_refcount > 1, it will release the DMA
43 * mapping and in-flight state accounting.
48 * the same page when a page is split. The API user must setup pool->p.max_len
49 * and pool->
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/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-linksys-wrv54g.dts1 // SPDX-License-Identifier: ISC
9 /dts-v1/;
11 #include "intel-ixp42x.dtsi"
12 #include <dt-bindings/input/input.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
28 stdout-path = "uart1:115200n8";
39 compatible = "gpio-leds";
40 led-power {
43 default-state = "on";
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/linux/block/
H A Dblk-mq.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/blk-mq.h>
6 #include "blk-stat.h"
17 * struct blk_mq_ctx - State for a software queue facing the submitting CPUs
25 unsigned int cpu; member
35 BLK_MQ_NO_TAG = -1U,
37 BLK_MQ_TAG_MAX = BLK_MQ_NO_TAG - 1,
73 * CPU -> queue mappings
78 * blk_mq_map_queue_type() - map (hctx_type,cpu) to hardware queue
81 * @cpu: CPU
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
11 chassis-type = "tablet";
16 pp1250_s3: regulator-pp1250-s3 {
17 compatible = "regulator-fixed";
18 regulator-name = "pp1250_s3";
21 regulator-always-on;
22 regulator-boot-on;
23 regulator-min-microvolt = <1250000>;
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/linux/net/netfilter/
H A Dnft_set_pipapo.h1 // SPDX-License-Identifier: GPL-2.0-only
8 /* Count of concatenated fields depends on count of 32-bit nftables registers */
25 #define NFT_PIPAPO_GROUPS_PER_BYTE(f) (BITS_PER_BYTE / (f)->bb)
32 * crossing page boundaries on most architectures (x86-64 and MIPS huge pages,
34 * keeps performance nice in case kvmalloc() gives us non-contiguous areas.
39 #define NFT_PIPAPO_LT_SIZE_LOW NFT_PIPAPO_LT_SIZE_THRESHOLD - \
44 (round_up((f)->group
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/linux/Documentation/networking/
H A Dnapi.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
30 of the NAPI instance while the method is the driver-specific event
37 -----------
55 ------------
64 argument - drivers can process completions for any number of Tx
96 or return ``budget - 1``.
101 -------------
109 As mentioned in the :ref:`drv_ctrl` section - napi_disable() and subsequent
118 --------------------------
121 the NAPI instance - until NAPI polling finishes any further
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H A Dtls-offload.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
13 For details regarding the user-facing interface refer to the TLS
18 * Software crypto mode (``TLS_SW``) - CPU handles the cryptography.
19 In most basic cases only crypto operations synchronous with the CPU
20 can be used, but depending on calling context CPU may utilize
24 * Packet-based NIC offload mode (``TLS_HW``) - the NIC handles crypto
28 (``ethtool`` flags ``tls-hw-tx-offload`` and ``tls-hw-rx-offload``).
29 * Full TCP NIC offload mode (``TLS_HW_RECORD``) - mode of operation where
33 abilities or QoS and packet scheduling (``ethtool`` flag ``tls-hw-record``).
36 offload opt-in or opt-out on per-connection basis is not currently supported.
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/linux/net/dsa/
H A Dswitch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2017 Savoir-faire Linux Inc.
29 if (dp->ageing_time && dp->ageing_time < ageing_time) in dsa_switch_fastest_ageing_time()
30 ageing_time = dp->ageing_time; in dsa_switch_fastest_ageing_time()
38 unsigned int ageing_time = info->ageing_time; in dsa_switch_ageing_time()
40 if (ds->ageing_time_min && ageing_time < ds->ageing_time_min) in dsa_switch_ageing_time()
41 return -ERANGE; in dsa_switch_ageing_time()
43 if (ds->ageing_time_max && ageing_time > ds->ageing_time_max) in dsa_switch_ageing_time()
44 return -ERANGE; in dsa_switch_ageing_time()
49 if (ds->ops->set_ageing_time) in dsa_switch_ageing_time()
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/linux/drivers/dma-buf/
H A Ddma-fence.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Fence mechanism for dma-buf and to allow for asynchronous dma access
16 #include <linux/dma-fence.h>
50 * Since the purposes of fences is to facilitate cross-device and
51 * cross-application synchronization, there's multiple ways to use one:
53 * - Individual fences can be exposed as a &sync_file, accessed as a file
58 * - Some subsystems also have their own explicit fencing primitives, like
62 * - Then there's also implicit fencing, where the synchronization points are
69 * DOC: fence cross-driver contract
77 * further command submission and force complete all in-flight fences, e.g.
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/linux/scripts/
H A Dcheck-uapi.sh2 # SPDX-License-Identifier: GPL-2.0-only
5 set -o errexit
6 set -o pipefail
11 $name - check for UAPI header stability across Git commits
15 check against additional commit ranges with the -b and -p options.
20 Usage: $name [-b BASE_REF] [-p PAST_REF] [-j N] [-l ERROR_LOG] [-i] [-q] [-v]
23 -b BASE_REF Base git reference to use for comparison. If unspecified or empty,
26 -p PAST_REF Compare BASE_REF to PAST_REF (e.g. -p v6.1). If unspecified or empty,
29 -j JOBS Number of checks to run in parallel (default: number of CPU cores).
30 -l ERROR_LOG Write error log to file (default: no error log is generated).
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/linux/drivers/net/dsa/realtek/
H A Drtl8365mb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
8 * integrated PHYs for the user facing ports, and an extension interface which
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
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H A Drtl8366rb.c1 // SPDX-License-Identifier: GPL-2.0
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
27 #include "realtek-smi.h"
28 #include "realtek-mdio.h"
47 /* Switch per-port learning disablement register */
120 /* CPU port control reg */
160 * VID such as untagged or priority-tagged frames for respective
163 * a C-tag with VID != 0 for respective port.
221 #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
363 mib->offset; in rtl8366rb_get_mib_counter()
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/linux/drivers/pci/
H A Dof.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI <-> OF mapping helpers
22 * pci_set_of_node - Find and set device's DT device_node
26 * DT. Returns -ENODEV if the device is present, but disabled in the DT.
30 if (!dev->bus->dev.of_node) in pci_set_of_node()
34 of_pci_find_child_device(dev->bus->dev.of_node, dev->devfn); in pci_set_of_node()
41 dev->bus->dev.of_node_reused = true; in pci_set_of_node()
43 device_set_node(&dev->dev, of_fwnode_handle(no_free_ptr(node))); in pci_set_of_node()
49 of_node_put(dev->dev.of_node); in pci_release_of_node()
50 device_set_node(&dev->dev, NULL); in pci_release_of_node()
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/linux/drivers/net/dsa/sja1105/
H A Dsja1105_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
76 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; in sja1105_is_vlan_configured()
77 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; in sja1105_is_vlan_configured()
84 return -1; in sja1105_is_vlan_configured()
89 struct sja1105_private *priv = ds->priv; in sja1105_drop_untagged()
92 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_drop_untagged()
107 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_pvid_apply()
122 struct sja1105_private *priv = ds->priv; in sja1105_commit_pvid()
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