Lines Matching +full:cpu +full:- +full:facing
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 the early-to-mid 2000s. The chip features a CPU port and four outgoing ports,
19 fabric, connected to an external MII interface name MII-P5. This is
20 unrelated from the CPU-facing port 5 which is used for DSA MII traffic.
25 - micrel,ks8995
26 - micrel,ksz8795
27 - micrel,ksz8864
32 reset-gpios:
37 - $ref: dsa.yaml#/$defs/ethernet-ports
38 - $ref: /schemas/spi/spi-peripheral-props.yaml#
41 - compatible
42 - reg
47 - |
48 #include <dt-bindings/gpio/gpio.h>
51 #address-cells = <1>;
52 #size-cells = <0>;
54 ethernet-switch@0 {
57 spi-max-frequency = <25000000>;
59 ethernet-ports {
60 #address-cells = <1>;
61 #size-cells = <0>;
63 ethernet-port@0 {
67 ethernet-port@1 {
71 ethernet-port@2 {
75 ethernet-port@3 {
79 ethernet-port@4 {
82 phy-mode = "mii";
83 fixed-link {
85 full-duplex;
93 #address-cells = <1>;
94 #size-cells = <1>;
96 /* The WAN port connected on MII-P5 */
97 ethernet-port@1000 {
100 phy-mode = "mii";
101 phy-handle = <&phy5>;
104 mac2: ethernet-port@2000 {
106 phy-mode = "mii";
107 fixed-link {
109 full-duplex;
115 #address-cells = <1>;
116 #size-cells = <0>;
118 /* LAN PHYs 1-4 accessible over external MDIO */
119 phy1: ethernet-phy@1 {
122 phy2: ethernet-phy@2 {
125 phy3: ethernet-phy@3 {
128 phy4: ethernet-phy@4 {
132 phy5: ethernet-phy@5 {