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/linux/drivers/clk/renesas/
H A DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
[all …]
H A Dr9a07g054.dtsi9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
356 clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
357 resets = <&cpg R9A07G054_GPT_RST_C>;
358 power-domains = <&cpg>;
370 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
[all …]
H A Dr9a07g044.dtsi9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
356 clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
357 resets = <&cpg R9A07G044_GPT_RST_C>;
358 power-domains = <&cpg>;
370 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
[all …]
H A Dr9a08g045.dtsi9 #include <dt-bindings/clock/r9a08g045-cpg.h>
69 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
111 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
113 power-domains = <&cpg>;
114 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
129 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
131 power-domains = <&cpg>;
132 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
147 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
149 power-domains = <&cpg>;
[all …]
H A Dr9a09g057.dtsi8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
66 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
76 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
86 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
96 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
247 clocks = <&cpg CPG_MOD 0x5>;
248 power-domains = <&cpg>;
249 resets = <&cpg 0x36>;
255 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
262 power-domains = <&cpg>;
[all …]
H A Dr9a09g011.dtsi9 #include <dt-bindings/clock/r9a09g011-cpg.h>
41 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
[all …]
H A Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
83 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
95 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
168 clocks = <&cpg CPG_MOD 402>;
170 resets = <&cpg 402>;
184 clocks = <&cpg CPG_MOD 912>;
186 resets = <&cpg 912>;
199 clocks = <&cpg CPG_MOD 911>;
201 resets = <&cpg 911>;
214 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
101 clocks = <&cpg CPG_MOD 402>;
103 resets = <&cpg 402>;
117 clocks = <&cpg CPG_MOD 912>;
119 resets = <&cpg 912>;
132 clocks = <&cpg CPG_MOD 911>;
134 resets = <&cpg 911>;
147 clocks = <&cpg CPG_MOD 910>;
149 resets = <&cpg 910>;
162 clocks = <&cpg CPG_MOD 909>;
[all …]
H A Dr8a77951.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
151 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
165 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
179 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
193 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
209 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
222 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
235 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
248 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
362 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
82 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
93 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
153 clocks = <&cpg CPG_MOD 402>;
155 resets = <&cpg 402>;
169 clocks = <&cpg CPG_MOD 912>;
171 resets = <&cpg 912>;
184 clocks = <&cpg CPG_MOD 911>;
186 resets = <&cpg 911>;
199 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr9a09g047.dtsi8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
66 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
76 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
86 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
96 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
247 clocks = <&cpg CPG_MOD 0x5>;
248 power-domains = <&cpg>;
249 resets = <&cpg 0x36>;
255 clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>;
262 power-domains = <&cpg>;
[all …]
H A Dr8a774a1.dtsi10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
129 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
157 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
169 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
181 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
193 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
278 clocks = <&cpg CPG_MOD 402>;
280 resets = <&cpg 402>;
294 clocks = <&cpg CPG_MOD 912>;
[all …]
H A Dr8a774b1.dtsi10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
83 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
94 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
162 clocks = <&cpg CPG_MOD 402>;
164 resets = <&cpg 402>;
178 clocks = <&cpg CPG_MOD 912>;
180 resets = <&cpg 912>;
193 clocks = <&cpg CPG_MOD 911>;
195 resets = <&cpg 911>;
208 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77960.dtsi8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
151 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
165 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
181 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
194 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
207 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
220 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
327 clocks = <&cpg CPG_MOD 402>;
329 resets = <&cpg 402>;
343 clocks = <&cpg CPG_MOD 912>;
[all …]
H A Dr8a77980.dtsi9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
44 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
54 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
64 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
136 clocks = <&cpg CPG_MOD 402>;
138 resets = <&cpg 402>;
152 clocks = <&cpg CPG_MOD 912>;
154 resets = <&cpg 912>;
167 clocks = <&cpg CPG_MOD 911>;
[all …]
H A Dr8a77965.dtsi11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
104 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
116 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
198 clocks = <&cpg CPG_MOD 402>;
200 resets = <&cpg 402>;
214 clocks = <&cpg CPG_MOD 912>;
216 resets = <&cpg 912>;
229 clocks = <&cpg CPG_MOD 911>;
231 resets = <&cpg 911>;
244 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a774e1.dtsi10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
136 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
164 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
194 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
207 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
220 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
233 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
342 clocks = <&cpg CPG_MOD 402>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-mssr.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
27 - renesas,r7s9210-cpg-mssr # RZ/A2
28 - renesas,r8a7742-cpg-mssr # RZ/G1H
29 - renesas,r8a7743-cpg-mssr # RZ/G1M
30 - renesas,r8a7744-cpg-mssr # RZ/G1N
31 - renesas,r8a7745-cpg-mssr # RZ/G1E
32 - renesas,r8a77470-cpg-mssr # RZ/G1C
33 - renesas,r8a774a1-cpg-mssr # RZ/G2M
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
71 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
134 clocks = <&cpg CPG_MOD 402>;
136 resets = <&cpg 402>;
150 clocks = <&cpg CPG_MOD 912>;
152 resets = <&cpg 912>;
165 clocks = <&cpg CPG_MOD 911>;
167 resets = <&cpg 911>;
180 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
124 clocks = <&cpg CPG_MOD 402>;
126 resets = <&cpg 402>;
140 clocks = <&cpg CPG_MOD 912>;
142 resets = <&cpg 912>;
155 clocks = <&cpg CPG_MOD 911>;
157 resets = <&cpg 911>;
170 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
77 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
167 clocks = <&cpg CPG_MOD 402>;
169 resets = <&cpg 402>;
183 clocks = <&cpg CPG_MOD 912>;
185 resets = <&cpg 912>;
198 clocks = <&cpg CPG_MOD 911>;
200 resets = <&cpg 911>;
213 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
95 clocks = <&cpg CPG_MOD 402>;
97 resets = <&cpg 402>;
111 clocks = <&cpg CPG_MOD 912>;
113 resets = <&cpg 912>;
126 clocks = <&cpg CPG_MOD 911>;
128 resets = <&cpg 911>;
141 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
122 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
144 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
166 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
178 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
190 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
202 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
280 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
69 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
152 clocks = <&cpg CPG_MOD 402>;
154 resets = <&cpg 402>;
168 clocks = <&cpg CPG_MOD 912>;
170 resets = <&cpg 912>;
183 clocks = <&cpg CPG_MOD 911>;
185 resets = <&cpg 911>;
198 clocks = <&cpg CPG_MOD 910>;
[all …]

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