| /linux/Documentation/devicetree/bindings/media/ |
| H A D | mediatek,mdp3-rsz.yaml | 80 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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| H A D | mediatek-mdp.txt | 62 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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| H A D | mediatek,mdp3-rdma.yaml | 163 <&mmsys CLK_MM_MDP_RSZ1>;
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6765-mm.c | 29 GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3),
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| H A D | clk-mt2701-mm.c | 46 GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12),
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| H A D | clk-mt8167-mm.c | 43 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5),
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| H A D | clk-mt8183-mm.c | 51 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
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| H A D | clk-mt6795-mm.c | 39 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
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| H A D | clk-mt6797-mm.c | 40 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),
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| H A D | clk-mt6779-mm.c | 51 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
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| H A D | clk-mt8173-mm.c | 43 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
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| H A D | clk-mt2712-mm.c | 50 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
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| /linux/include/dt-bindings/clock/ |
| H A D | mt8167-clk.h | 84 #define CLK_MM_MDP_RSZ1 5 macro
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| H A D | mt6797-clk.h | 222 #define CLK_MM_MDP_RSZ1 8 macro
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| H A D | mediatek,mt6795-clk.h | 225 #define CLK_MM_MDP_RSZ1 6 macro
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| H A D | mt8173-clk.h | 254 #define CLK_MM_MDP_RSZ1 7 macro
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| H A D | mt6765-clk.h | 254 #define CLK_MM_MDP_RSZ1 3 macro
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| H A D | mt8183-clk.h | 324 #define CLK_MM_MDP_RSZ1 15 macro
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| H A D | mt2712-clk.h | 307 #define CLK_MM_MDP_RSZ1 6 macro
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| H A D | mt6779-clk.h | 356 #define CLK_MM_MDP_RSZ1 16 macro
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| H A D | mt2701-clk.h | 365 #define CLK_MM_MDP_RSZ1 13 macro
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8183.dtsi | 1679 <&mmsys CLK_MM_MDP_RSZ1>;
1701 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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| H A D | mt8173.dtsi | 1039 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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