| /linux/Documentation/devicetree/bindings/media/ |
| H A D | mediatek,mdp3-rsz.yaml | 71 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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| H A D | mediatek-mdp.txt | 55 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6765-mm.c | 28 GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_ck", 2),
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| H A D | clk-mt2701-mm.c | 47 GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13),
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| H A D | clk-mt8167-mm.c | 42 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4),
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| H A D | clk-mt8183-mm.c | 50 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
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| H A D | clk-mt6795-mm.c | 38 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
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| H A D | clk-mt6797-mm.c | 39 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6),
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| H A D | clk-mt6779-mm.c | 50 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
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| H A D | clk-mt8173-mm.c | 42 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
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| H A D | clk-mt2712-mm.c | 49 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
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| /linux/include/dt-bindings/clock/ |
| H A D | mt8167-clk.h | 83 #define CLK_MM_MDP_RSZ0 4 macro
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| H A D | mt6797-clk.h | 221 #define CLK_MM_MDP_RSZ0 7 macro
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| H A D | mediatek,mt6795-clk.h | 224 #define CLK_MM_MDP_RSZ0 5 macro
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| H A D | mt8173-clk.h | 253 #define CLK_MM_MDP_RSZ0 6 macro
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| H A D | mt6765-clk.h | 253 #define CLK_MM_MDP_RSZ0 2 macro
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| H A D | mt8183-clk.h | 323 #define CLK_MM_MDP_RSZ0 14 macro
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| H A D | mt2712-clk.h | 306 #define CLK_MM_MDP_RSZ0 5 macro
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| H A D | mt6779-clk.h | 355 #define CLK_MM_MDP_RSZ0 15 macro
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| H A D | mt2701-clk.h | 366 #define CLK_MM_MDP_RSZ0 14 macro
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8173.dtsi | 1032 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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| H A D | mt8183.dtsi | 1692 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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