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/freebsd/sys/dev/usb/controller/
H A Dusb_controller.c40 #include <sys/bus.h>
153 usb_root_mount_rel(struct usb_bus *bus) in usb_root_mount_rel() argument
155 if (bus->bus_roothold != NULL) { in usb_root_mount_rel()
156 DPRINTF("Releasing root mount hold %p\n", bus->bus_roothold); in usb_root_mount_rel()
157 root_mount_rel(bus->bus_roothold); in usb_root_mount_rel()
158 bus->bus_roothold = NULL; in usb_root_mount_rel()
169 struct usb_bus *bus = device_get_ivars(dev); in usb_attach() local
173 if (bus == NULL) { in usb_attach()
180 /* delay vfs_mountroot until the bus is explored */ in usb_attach()
181 bus->bus_roothold = root_mount_hold(device_get_nameunit(dev)); in usb_attach()
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/freebsd/sys/dev/ppbus/
H A Dppb_1284.c42 #include <sys/bus.h>
59 do_1284_wait(device_t bus, uint8_t mask, uint8_t status) in do_1284_wait() argument
61 return (ppb_poll_bus(bus, 4, mask, status, PPB_NOINTR | PPB_POLL)); in do_1284_wait()
65 do_peripheral_wait(device_t bus, uint8_t mask, uint8_t status) in do_peripheral_wait() argument
67 return (ppb_poll_bus(bus, 100, mask, status, PPB_NOINTR | PPB_POLL)); in do_peripheral_wait()
78 ppb_1284_reset_error(device_t bus, int state) in ppb_1284_reset_error() argument
80 struct ppb_data *ppb = DEVTOSOFTC(bus); in ppb_1284_reset_error()
94 ppb_1284_get_state(device_t bus) in ppb_1284_get_state() argument
96 struct ppb_data *ppb = DEVTOSOFTC(bus); in ppb_1284_get_state()
108 ppb_1284_set_state(device_t bus, int state) in ppb_1284_set_state() argument
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H A Dppb_base.c35 #include <sys/bus.h>
50 * Polls the bus
55 ppb_poll_bus(device_t bus, int max, in ppb_poll_bus() argument
58 struct ppb_data *ppb = DEVTOSOFTC(bus); in ppb_poll_bus()
62 ppb_assert_locked(bus); in ppb_poll_bus()
67 r = ppb_rstr(bus); in ppb_poll_bus()
76 if ((ppb_rstr(bus) & mask) == status) in ppb_poll_bus()
80 error = mtx_sleep((caddr_t)bus, ppb->ppc_lock, PPBPRI | in ppb_poll_bus()
96 ppb_get_epp_protocol(device_t bus) in ppb_get_epp_protocol() argument
100 ppb_assert_locked(bus); in ppb_get_epp_protocol()
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H A Dppbconf.c40 #include <sys/bus.h>
53 static MALLOC_DEFINE(M_PPBUSDEV, "ppbusdev", "Parallel Port bus device");
62 ppbus_print_child(device_t bus, device_t dev) in ppbus_print_child() argument
67 retval = bus_print_child_header(bus, dev); in ppbus_print_child()
74 retval += bus_print_child_footer(bus, dev); in ppbus_print_child()
82 device_set_desc(dev, "Parallel port bus"); in ppbus_probe()
107 /* add the device as a child to the ppbus bus with the allocated in ppbus_add_child()
116 ppbus_read_ivar(device_t bus, device_t dev, int index, uintptr_t* val) in ppbus_read_ivar() argument
122 *val = (u_long)ppb_get_mode(bus); in ppbus_read_ivar()
132 ppbus_write_ivar(device_t bus, device_t dev, int index, uintptr_t val) in ppbus_write_ivar() argument
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/freebsd/sys/dev/iicbus/
H A Diiconf.c35 #include <sys/bus.h>
44 * system errno value later. This lets controller- and bus-layer code get
94 iicbus_intr(device_t bus, int event, char *buf) in iicbus_intr() argument
96 struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); in iicbus_intr()
135 iicbus_request_bus(device_t bus, device_t dev, int how) in iicbus_request_bus() argument
138 struct iicbus_softc *sc = (struct iicbus_softc *)device_get_softc(bus); in iicbus_request_bus()
157 * Mark the device busy while it owns the bus, to in iicbus_request_bus()
158 * prevent detaching the device, bus, or hardware in iicbus_request_bus()
161 * attaching, it cannot be busied; mark the bus busy. in iicbus_request_bus()
164 sc->busydev = bus; in iicbus_request_bus()
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/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Dibm-power9-dual.dtsi22 cfam0_i2c0: i2c-bus@0 {
26 cfam0_i2c1: i2c-bus@1 {
30 cfam0_i2c2: i2c-bus@2 {
34 cfam0_i2c3: i2c-bus@3 {
38 cfam0_i2c4: i2c-bus@4 {
42 cfam0_i2c5: i2c-bus@5 {
46 cfam0_i2c6: i2c-bus@6 {
50 cfam0_i2c7: i2c-bus@7 {
54 cfam0_i2c8: i2c-bus@8 {
58 cfam0_i2c9: i2c-bus@9 {
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/freebsd/sys/dev/ofw/
H A Dofw_bus_if.m29 # properties of a device on an Open Firmware assisted bus for use
32 # as they are expected to be only of interest in the respective bus
35 #include <sys/bus.h>
62 ofw_bus_default_get_devinfo(device_t bus, device_t dev)
69 ofw_bus_default_get_compat(device_t bus, device_t dev)
76 ofw_bus_default_get_model(device_t bus, device_t dev)
83 ofw_bus_default_get_name(device_t bus, device_t dev)
90 ofw_bus_default_get_node(device_t bus, device_t dev)
97 ofw_bus_default_get_type(device_t bus, device_t dev)
104 ofw_bus_default_map_intr(device_t bus, device_t dev, phandle_t iparent,
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/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dsamsung,exynos-bus.yaml4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
18 monitor the usage of each bus in runtime, the driver uses the PPMU (Platform
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
23 The each AXI bus has the owned source clock but, has not the only owned power
26 type of bus devices as following::
27 - parent bus device
28 - passive bus device
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/freebsd/lib/libpmc/pmu-events/arch/x86/bonnell/
H A Dother.json3 "BriefDescription": "Bus queue is empty.",
11 "BriefDescription": "Number of Bus Not Ready signals asserted.",
19 "BriefDescription": "Number of Bus Not Ready signals asserted.",
27 "BriefDescription": "Bus cycles while processor receives data.",
35 "BriefDescription": "Bus cycles when data is sent on the bus.",
43 "BriefDescription": "Bus cycles when data is sent on the bus.",
83 "BriefDescription": "IO requests waiting in the bus queue.",
91 "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
99 "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
107 "BriefDescription": "Outstanding cacheable data read bus requests duration.",
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/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Dexynos-bus.txt1 * Generic Exynos Bus frequency device
5 for buses. Generally, each bus of Exynos SoC includes a source clock
7 of the bus in runtime. To monitor the usage of each bus in runtime,
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
12 The each AXI bus has the owned source clock but, has not the only owned
15 There are two type of bus devices as following:
16 - parent bus device
17 - passive bus device
19 Basically, parent and passive bus device share the same power line.
20 The parent bus device can only change the voltage of shared power line
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/freebsd/sys/amd64/pci/
H A Dpci_cfgreg.c33 #include <sys/bus.h>
52 static uint32_t pci_docfgregread(int domain, int bus, int slot, int func,
54 static struct pcie_mcfg_region *pcie_lookup_region(int domain, int bus);
55 static int pciereg_cfgread(struct pcie_mcfg_region *region, int bus,
57 static void pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus,
60 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
61 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
90 pcie_lookup_region(int domain, int bus) in pcie_lookup_region() argument
94 bus >= mcfg_regions[i].minbus && in pcie_lookup_region()
95 bus <= mcfg_regions[i].maxbus) in pcie_lookup_region()
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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dsimple-pm-bus.yaml4 $id: http://devicetree.org/schemas/bus/simple-pm-bus.yaml#
7 title: Simple Power-Managed Bus
13 A Simple Power-Managed Bus is a transparent bus that doesn't need a real
16 However, its bus controller is part of a PM domain, or under the control
17 of a functional clock. Hence, the bus controller's PM domain and/or
18 clock must be enabled for child devices connected to the bus (either
21 While "simple-pm-bus" follows the "simple-bus" set of properties, as
23 "simple-bus".
27 pattern: "^bus(@[0-9a-f]+)?$"
31 const: simple-pm-bus
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H A Dfsl,spba-bus.yaml4 $id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml#
7 title: Shared Peripherals Bus Interface
13 A simple bus enabling access to shared peripherals.
15 The "spba-bus" follows the "simple-bus" set of properties, as
17 "simple-bus" because the SDMA controller uses this compatible flag to
19 the SDMA can access. There are no special clocks for the bus, because
26 const: fsl,spba-bus
32 pattern: "^spba-bus(@[0-9a-f]+)?$"
36 - const: fsl,spba-bus
37 - const: simple-bus
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H A Dsocionext,uniphier-system-bus.yaml4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
7 title: UniPhier System Bus
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
14 Before any access to the bus, the bus controller must be configured; the bus
18 be optimized for faster bus access.
25 const: socionext,uniphier-system-bus
41 Provide address translation from the System Bus to the parent bus.
44 The address region(s) that can be assigned for the System Bus is
58 work. The software should initialize the bus controller according to it.
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/freebsd/share/man/man9/
H A Dbus_space.9143 .Nd "bus space manipulation functions"
627 machine-independent access to bus memory and register areas.
648 object file to manipulate a set of devices on multiple bus types on a
653 supported by the bus.
670 Bus spaces are described by bus space tags, which can be created only by
673 of bus space (e.g.\& memory space and I/O space), and thus may provide
674 multiple different bus space tags.
675 Individual buses or devices on a machine may use more than one bus space
681 space, for instance because of multiple different host bus interface
684 A range in bus space is described by a bus address and a bus size.
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/freebsd/sys/dev/smbus/
H A Dsmbconf.h56 * SMB bus errors
97 #define smbus_quick(bus,slave,how) \ argument
98 (SMBUS_QUICK(device_get_parent(bus), slave, how))
99 #define smbus_sendb(bus,slave,byte) \ argument
100 (SMBUS_SENDB(device_get_parent(bus), slave, byte))
101 #define smbus_recvb(bus,slave,byte) \ argument
102 (SMBUS_RECVB(device_get_parent(bus), slave, byte))
103 #define smbus_writeb(bus,slave,cmd,byte) \ argument
104 (SMBUS_WRITEB(device_get_parent(bus), slave, cmd, byte))
105 #define smbus_writew(bus,slave,cmd,word) \ argument
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/freebsd/sys/x86/pci/
H A Dpci_bus.c34 #include <sys/bus.h>
63 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, in legacy_pcib_read_config() argument
66 return(pci_cfgregread(0, bus, slot, func, reg, bytes)); in legacy_pcib_read_config()
72 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, in legacy_pcib_write_config() argument
75 pci_cfgregwrite(0, bus, slot, func, reg, data, bytes); in legacy_pcib_write_config()
99 device_t bus; in legacy_pcib_alloc_msi() local
101 bus = device_get_parent(pcib); in legacy_pcib_alloc_msi()
102 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, in legacy_pcib_alloc_msi()
109 device_t bus; in legacy_pcib_alloc_msix() local
111 bus = device_get_parent(pcib); in legacy_pcib_alloc_msix()
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H A Dqpi.c31 * This driver provides a pseudo-bus to enumerate the PCI buses
32 * present on a system using a QPI chipset. It creates a qpi0 bus that
38 #include <sys/bus.h>
82 /* Add a qpi bus device. */ in qpi_identify()
84 panic("Failed to add qpi bus"); in qpi_identify()
91 device_set_desc(dev, "QPI system bus"); in qpi_probe()
96 * Look for a PCI bus with the specified bus address. If one is found,
100 qpi_probe_pcib(device_t dev, int bus) in qpi_probe_pcib() argument
108 * If a PCI bus already exists for this bus number, then in qpi_probe_pcib()
111 if (pci_find_bsf(bus, 0, 0) != NULL) in qpi_probe_pcib()
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/freebsd/sys/dev/mdio/
H A Dmdio_if.m2 #include <sys/bus.h>
29 * @brief Read register from device on MDIO bus.
31 * @param dev MDIO bus device.
42 * @brief Read register from device on MDIO muxed bus.
44 * @param dev MDIO bus device.
45 * @param bus MDIO bus mux position
51 int bus;
57 * @brief Write register to device on MDIO bus.
59 * @param dev MDIO bus device.
72 * @brief Write register to device on MDIO muxed bus.
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/freebsd/sys/xen/xenbus/
H A Dxenbusb.h42 * bus attachements (e.g. frontend and backend device buses) for XenBus.
55 * \brief Container for all state needed to manage a Xenbus Bus
61 * XenStore where devices for this bus attachment arrive
86 * The number of children for this bus that are still
92 /** The NewBus device_t for this bus attachment. */
97 * bus attachment manages.
103 * character) that make up the device ID on this bus.
115 * count of its parent bus.
120 /** Instance variables for devices on a XenBus bus. */
185 * \brief Perform common XenBus bus attach processing.
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/freebsd/share/man/man4/
H A Diicbus.430 .Nd I2C bus system
45 I2C is an acronym for Inter Integrated Circuit bus.
46 The I2C bus was developed
51 The BUS physically consists of 2 active wires and a ground connection.
56 Every component hooked up to the bus has its own unique address whether it
63 more BUS MASTERs.
65 The BUS MASTER is the chip issuing the commands on the BUS.
68 bus is considered the BUS MASTER.
70 as the BUS SLAVEs.
71 As mentioned before, the IC bus is a Multi-MASTER BUS.
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H A Diicmux.432 .Nd I2C bus mulitiplexer framework
55 I2C bus multiplexer (mux) hardware.
64 Generally speaking, an I2C mux is connected to an upstream I2C bus, and to
66 any one of the downstream buses to the upstream bus.
75 the active downstream bus.
84 downstream bus (if any) should be connected while in the idle state.
85 In the absence of such configuration, whichever downstream bus was
86 last used remains connected to the upstream bus.
88 When an I2C slave device on a bus downstream of a mux initiates I/O,
89 it first requests exclusive use of the bus by calling
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/freebsd/sys/contrib/device-tree/Bindings/arm/omap/
H A Dl4.txt3 These bindings describe the OMAP SoCs L4 interconnect bus.
6 - compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
7 Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
8 Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
9 Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
10 Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
11 Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
12 Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
13 Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
14 Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
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/freebsd/sys/powerpc/ps3/
H A Dps3-hvcall.master97 HVCALL 170 lv1_open_device bus,dev,zero
98 HVCALL 171 lv1_close_device bus,dev
99 HVCALL 172 lv1_map_device_mmio_region bus,dev,bus_addr,size,page_size lpar_addr
100 HVCALL 173 lv1_unmap_device_mmio_region bus,dev,lpar_addr
101 HVCALL 174 lv1_allocate_device_dma_region bus,dev,io_size,io_pagesize,flag dma_region
102 HVCALL 175 lv1_free_device_dma_region bus,dev,dma_region
103 HVCALL 176 lv1_map_device_dma_region bus,dev,lpar_addr,dma_region,size,flags
104 HVCALL 177 lv1_unmap_device_dma_region bus,dev,dma_region,size
105 HVCALL 178 lv1_read_pci_config ps3bus,bus,dev,func,offset,size result
106 HVCALL 179 lv1_write_pci_config ps3bus,bus,dev,func,offset,size,data
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-bus.dtsi3 * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
35 compatible = "samsung,exynos-bus";
37 clock-names = "bus";
43 compatible = "samsung,exynos-bus";
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