Lines Matching full:bus
33 #include <sys/bus.h>
52 static uint32_t pci_docfgregread(int domain, int bus, int slot, int func,
54 static struct pcie_mcfg_region *pcie_lookup_region(int domain, int bus);
55 static int pciereg_cfgread(struct pcie_mcfg_region *region, int bus,
57 static void pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus,
60 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
61 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
90 pcie_lookup_region(int domain, int bus) in pcie_lookup_region() argument
94 bus >= mcfg_regions[i].minbus && in pcie_lookup_region()
95 bus <= mcfg_regions[i].maxbus) in pcie_lookup_region()
101 pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes) in pci_docfgregread() argument
103 if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0) in pci_docfgregread()
104 return (pcireg_cfgread(bus, slot, func, reg, bytes)); in pci_docfgregread()
109 region = pcie_lookup_region(domain, bus); in pci_docfgregread()
111 return (pciereg_cfgread(region, bus, slot, func, reg, in pci_docfgregread()
116 return (pcireg_cfgread(bus, slot, func, reg, bytes)); in pci_docfgregread()
125 pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes) in pci_cfgregread() argument
138 line = pci_docfgregread(domain, bus, slot, func, PCIR_INTLINE, in pci_cfgregread()
144 return (pci_docfgregread(domain, bus, slot, func, reg, bytes)); in pci_cfgregread()
151 pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data, in pci_cfgregwrite() argument
154 if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0) { in pci_cfgregwrite()
155 pcireg_cfgwrite(bus, slot, func, reg, data, bytes); in pci_cfgregwrite()
162 region = pcie_lookup_region(domain, bus); in pci_cfgregwrite()
164 pciereg_cfgwrite(region, bus, slot, func, reg, data, in pci_cfgregwrite()
171 pcireg_cfgwrite(bus, slot, func, reg, data, bytes); in pci_cfgregwrite()
180 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes) in pci_cfgenable() argument
184 if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX && in pci_cfgenable()
187 outl(CONF1_ADDR_PORT, (1U << 31) | (bus << 16) | (slot << 11) in pci_cfgenable()
206 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes) in pcireg_cfgread() argument
212 port = pci_cfgenable(bus, slot, func, reg, bytes); in pcireg_cfgread()
232 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) in pcireg_cfgwrite() argument
237 port = pci_cfgenable(bus, slot, func, reg, bytes); in pcireg_cfgwrite()
262 * On some AMD systems, some of the devices on bus 0 are in pcie_init_badslots()
264 * bus 0 looking for such devices. For these devices, we will in pcie_init_badslots()
289 printf("PCI: MCFG domain %u bus %u-%u base @ 0x%lx\n", in pcie_cfgregopen()
313 #define PCIE_VADDR(base, reg, bus, slot, func) \ argument
315 ((((bus) & 0xff) << 20) | \
329 pciereg_cfgread(struct pcie_mcfg_region *region, int bus, unsigned slot, in pciereg_cfgread() argument
335 MPASS(bus >= region->minbus && bus <= region->maxbus); in pciereg_cfgread()
340 va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func); in pciereg_cfgread()
361 pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus, unsigned slot, in pciereg_cfgwrite() argument
366 MPASS(bus >= region->minbus && bus <= region->maxbus); in pciereg_cfgwrite()
371 va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func); in pciereg_cfgwrite()