171e8eac4SAdrian Chadd 271e8eac4SAdrian Chadd#include <sys/bus.h> 371e8eac4SAdrian Chadd 471e8eac4SAdrian ChaddINTERFACE mdio; 571e8eac4SAdrian Chadd 6e2db1d1fSAdrian ChaddCODE { 7e2db1d1fSAdrian Chadd #include <dev/mdio/mdio.h> 8e2db1d1fSAdrian Chadd 9e2db1d1fSAdrian Chadd static int 10e2db1d1fSAdrian Chadd mdio_null_readextreg(device_t dev, int phy, int devad, int reg) 11e2db1d1fSAdrian Chadd { 12e2db1d1fSAdrian Chadd if (devad == MDIO_DEVADDR_NONE) 13e2db1d1fSAdrian Chadd return (MDIO_READREG(dev, phy, reg)); 14e2db1d1fSAdrian Chadd return (~0U); 15e2db1d1fSAdrian Chadd } 16e2db1d1fSAdrian Chadd 17e2db1d1fSAdrian Chadd static int 18e2db1d1fSAdrian Chadd mdio_null_writeextreg(device_t dev, int phy, int devad, int reg, 19e2db1d1fSAdrian Chadd int val) 20e2db1d1fSAdrian Chadd { 21e2db1d1fSAdrian Chadd if (devad == MDIO_DEVADDR_NONE) 22e2db1d1fSAdrian Chadd return (MDIO_WRITEREG(dev, phy, reg, val)); 23e2db1d1fSAdrian Chadd 24e2db1d1fSAdrian Chadd return (EINVAL); 25e2db1d1fSAdrian Chadd } 26e2db1d1fSAdrian Chadd} 27e2db1d1fSAdrian Chadd 28e2db1d1fSAdrian Chadd/** 29e2db1d1fSAdrian Chadd * @brief Read register from device on MDIO bus. 30e2db1d1fSAdrian Chadd * 31e2db1d1fSAdrian Chadd * @param dev MDIO bus device. 32e2db1d1fSAdrian Chadd * @param phy PHY address. 33e2db1d1fSAdrian Chadd * @param reg The PHY register offset. 34e2db1d1fSAdrian Chadd */ 3571e8eac4SAdrian ChaddMETHOD int readreg { 3671e8eac4SAdrian Chadd device_t dev; 3771e8eac4SAdrian Chadd int phy; 3871e8eac4SAdrian Chadd int reg; 3971e8eac4SAdrian Chadd}; 4071e8eac4SAdrian Chadd 41e2db1d1fSAdrian Chadd/** 42*36c1a376SWojciech Macek * @brief Read register from device on MDIO muxed bus. 43*36c1a376SWojciech Macek * 44*36c1a376SWojciech Macek * @param dev MDIO bus device. 45*36c1a376SWojciech Macek * @param bus MDIO bus mux position 46*36c1a376SWojciech Macek * @param phy PHY address. 47*36c1a376SWojciech Macek * @param reg The PHY register offset. 48*36c1a376SWojciech Macek */ 49*36c1a376SWojciech MacekMETHOD int readreg_mux { 50*36c1a376SWojciech Macek device_t dev; 51*36c1a376SWojciech Macek int bus; 52*36c1a376SWojciech Macek int phy; 53*36c1a376SWojciech Macek int reg; 54*36c1a376SWojciech Macek}; 55*36c1a376SWojciech Macek 56*36c1a376SWojciech Macek/** 57e2db1d1fSAdrian Chadd * @brief Write register to device on MDIO bus. 58e2db1d1fSAdrian Chadd * 59e2db1d1fSAdrian Chadd * @param dev MDIO bus device. 60e2db1d1fSAdrian Chadd * @param phy PHY address. 61e2db1d1fSAdrian Chadd * @param reg The PHY register offset. 62e2db1d1fSAdrian Chadd * @param val The value to write at offset @p reg. 63e2db1d1fSAdrian Chadd */ 6471e8eac4SAdrian ChaddMETHOD int writereg { 6571e8eac4SAdrian Chadd device_t dev; 6671e8eac4SAdrian Chadd int phy; 6771e8eac4SAdrian Chadd int reg; 6871e8eac4SAdrian Chadd int val; 6971e8eac4SAdrian Chadd}; 70e2db1d1fSAdrian Chadd 71*36c1a376SWojciech Macek/** 72*36c1a376SWojciech Macek * @brief Write register to device on MDIO muxed bus. 73*36c1a376SWojciech Macek * 74*36c1a376SWojciech Macek * @param dev MDIO bus device. 75*36c1a376SWojciech Macek * @param bus MDIO bus mux position 76*36c1a376SWojciech Macek * @param phy PHY address. 77*36c1a376SWojciech Macek * @param reg The PHY register offset. 78*36c1a376SWojciech Macek * @param val The value to write at offset @p reg. 79*36c1a376SWojciech Macek */ 80*36c1a376SWojciech MacekMETHOD int writereg_mux { 81*36c1a376SWojciech Macek device_t dev; 82*36c1a376SWojciech Macek int bus; 83*36c1a376SWojciech Macek int phy; 84*36c1a376SWojciech Macek int reg; 85*36c1a376SWojciech Macek int val; 86*36c1a376SWojciech Macek}; 87*36c1a376SWojciech Macek 88e2db1d1fSAdrian Chadd 89e2db1d1fSAdrian Chadd/** 90e2db1d1fSAdrian Chadd * @brief Read extended register from device on MDIO bus. 91e2db1d1fSAdrian Chadd * 92e2db1d1fSAdrian Chadd * @param dev MDIO bus device. 93e2db1d1fSAdrian Chadd * @param phy PHY address. 94e2db1d1fSAdrian Chadd * @param devad The MDIO IEEE 802.3 Clause 45 device address, or 95e2db1d1fSAdrian Chadd * MDIO_DEVADDR_NONE to request Clause 22 register addressing. 96e2db1d1fSAdrian Chadd * @param reg The PHY register offset. 97e2db1d1fSAdrian Chadd */ 98e2db1d1fSAdrian ChaddMETHOD int readextreg { 99e2db1d1fSAdrian Chadd device_t dev; 100e2db1d1fSAdrian Chadd int phy; 101e2db1d1fSAdrian Chadd int devad; 102e2db1d1fSAdrian Chadd int reg; 103e2db1d1fSAdrian Chadd} DEFAULT mdio_null_readextreg; 104e2db1d1fSAdrian Chadd 105e2db1d1fSAdrian Chadd 106e2db1d1fSAdrian Chadd/** 107e2db1d1fSAdrian Chadd * @brief Write extended register to device on MDIO bus. 108e2db1d1fSAdrian Chadd * 109e2db1d1fSAdrian Chadd * @param dev MDIO bus device. 110e2db1d1fSAdrian Chadd * @param phy PHY address. 111e2db1d1fSAdrian Chadd * @param devad The MDIO IEEE 802.3 Clause 45 device address, or 112e2db1d1fSAdrian Chadd * MDIO_DEVADDR_NONE to request Clause 22 register addressing. 113e2db1d1fSAdrian Chadd * @param reg The PHY register offset. 114e2db1d1fSAdrian Chadd * @param val The value to write at offset @p reg. 115e2db1d1fSAdrian Chadd */ 116e2db1d1fSAdrian ChaddMETHOD int writeextreg { 117e2db1d1fSAdrian Chadd device_t dev; 118e2db1d1fSAdrian Chadd int phy; 119e2db1d1fSAdrian Chadd int devad; 120e2db1d1fSAdrian Chadd int reg; 121e2db1d1fSAdrian Chadd int val; 122e2db1d1fSAdrian Chadd} DEFAULT mdio_null_writeextreg; 123