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/linux/drivers/net/ethernet/neterion/
H A Ds2io.c1010 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_verify_pci_mode() local
1014 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1044 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_print_pci_mode() local
1050 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1114 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_tti() local
1138 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1163 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1168 writeq(val64, &bar0->tti_command_mem); in init_tti()
1170 if (wait_for_cmd_complete(&bar0->tti_command_mem, in init_tti()
1190 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_nic() local
[all …]
/linux/drivers/gpu/nova-core/fb/hal/
H A Dtu102.rs3 use crate::driver::Bar0;
12 pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 { in read_sysmem_flush_page_gm107()
16 pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result { in write_sysmem_flush_page_gm107() argument
29 pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool { in display_enabled_gm107()
33 pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 { in vidmem_size_gp102()
40 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { in read_sysmem_flush_page()
44 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { in write_sysmem_flush_page() argument
48 fn supports_display(&self, bar: &Bar0) -> bool { in supports_display()
52 fn vidmem_size(&self, bar: &Bar0) -> u64 { in vidmem_size()
H A Dga100.rs7 use crate::driver::Bar0;
13 pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 { in read_sysmem_flush_page_ga100()
19 pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) { in write_sysmem_flush_page_ga100() argument
28 pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool { in display_enabled_ga100()
37 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { in read_sysmem_flush_page()
41 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { in write_sysmem_flush_page() argument
47 fn supports_display(&self, bar: &Bar0) -> bool { in supports_display()
51 fn vidmem_size(&self, bar: &Bar0) -> u64 { in vidmem_size()
H A Dga102.rs5 use crate::driver::Bar0;
9 fn vidmem_size_ga102(bar: &Bar0) -> u64 { in vidmem_size_ga102()
16 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { in read_sysmem_flush_page()
20 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { in write_sysmem_flush_page() argument
26 fn supports_display(&self, bar: &Bar0) -> bool { in supports_display()
30 fn vidmem_size(&self, bar: &Bar0) -> u64 { in vidmem_size()
/linux/sound/pci/lola/
H A Dlola.c92 lola_writew(chip, BAR0, CORBWP, wp); in corb_send_verb()
112 wp = lola_readw(chip, BAR0, RIRBWP); in lola_update_rirb()
262 rbsts = lola_readb(chip, BAR0, RIRBSTS); in lola_interrupt()
265 lola_writeb(chip, BAR0, RIRBSTS, rbsts); in lola_interrupt()
266 rbsts = lola_readb(chip, BAR0, CORBSTS); in lola_interrupt()
269 lola_writeb(chip, BAR0, CORBSTS, rbsts); in lola_interrupt()
295 unsigned int gctl = lola_readl(chip, BAR0, GCTL); in reset_controller()
305 lola_writel(chip, BAR0, GCTL, LOLA_GCTL_RESET); in reset_controller()
309 gctl = lola_readl(chip, BAR0, GCTL); in reset_controller()
359 lola_writeb(chip, BAR0, RIRBCT in setup_corb_rirb()
[all...]
/linux/Documentation/misc-devices/
H A Dspear-pcie-gadget.rst46 bar0_size: returns size of bar0 in hex.
47 bar0_address returns address of bar0 mapped area in hex.
48 bar0_rw_offset returns offset of bar0 for which bar0_data will return value.
65 bar0_size write size of bar0 in hex. default bar0 size is 1000 (hex)
67 bar0_address write address of bar0 mapped area in hex. (default mapping of
68 bar0 is SYSRAM1(E0800000). Always program bar size before bar
71 bar0_rw_offset write offset of bar0 for which bar0_data will write value.
98 program BAR0 size as 1MB::
102 check for programmed bar0 size::
106 Program BAR0 Address as DDR (0x2100000). This is the physical address of
[all …]
/linux/drivers/gpu/nova-core/fb/
H A Dhal.rs5 use crate::driver::Bar0;
14 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64; in read_sysmem_flush_page()
19 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result; in write_sysmem_flush_page() argument
22 fn supports_display(&self, bar: &Bar0) -> bool; in supports_display()
25 fn vidmem_size(&self, bar: &Bar0) -> u64; in vidmem_size()
/linux/drivers/platform/x86/
H A Dp2sb.c33 * Cache BAR0 of P2SB device functions 0 to 7.
68 struct resource *bar0 = pci_resource_n(pdev, 0); in p2sb_read_bar0() local
78 mem->start = bar0->start; in p2sb_read_bar0()
79 mem->end = bar0->end; in p2sb_read_bar0()
80 mem->flags = bar0->flags; in p2sb_read_bar0()
81 mem->desc = bar0->desc; in p2sb_read_bar0()
107 /* Scan the P2SB device and cache its BAR0 */ in p2sb_scan_and_cache()
/linux/Documentation/scsi/
H A Dhptiop.rst11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
14 BAR0 offset Register
36 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
39 BAR0 offset Register
54 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
57 BAR0 offset Register
78 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
81 BAR0 offset Register
119 relative to the IOP BAR0.
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dshadowramin.c27 u32 bar0; member
49 nvkm_wr32(device, 0x001700, priv->bar0); in pramin_fini()
104 /* modify bar0 PRAMIN window to cover the bios image */ in pramin_init()
111 priv->bar0 = nvkm_rd32(device, 0x001700); in pramin_init()
/linux/include/linux/usb/
H A Dnet2280.h24 /* main registers, BAR0 + 0x0000 */
227 /* usb control, BAR0 + 0x0080 */
291 /* pci control, BAR0 + 0x0100 */
318 /* dma control, BAR0 + 0x0180 ... array of four structs like this,
360 /* dedicated endpoint registers, BAR0 + 0x0200 */
370 /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
/linux/drivers/scsi/snic/
H A Dsnic_main.c260 if (snic->bar0.vaddr) in snic_iounmap()
261 iounmap(snic->bar0.vaddr); in snic_iounmap()
428 /* Map vNIC resources from BAR0 */ in snic_probe()
430 SNIC_HOST_ERR(shost, "BAR0 not memory mappable aborting.\n"); in snic_probe()
436 snic->bar0.vaddr = pci_iomap(pdev, 0, 0); in snic_probe()
437 if (!snic->bar0.vaddr) { in snic_probe()
439 "Cannot memory map BAR0 res hdr aborting.\n"); in snic_probe()
445 snic->bar0.bus_addr = pci_resource_start(pdev, 0); in snic_probe()
446 snic->bar0.len = pci_resource_len(pdev, 0); in snic_probe()
447 SNIC_BUG_ON(snic->bar0.bus_addr == 0); in snic_probe()
[all …]
/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hw.h37 /* Read from an address offset from BAR0, existing registers */
41 /* Write to an address offset from BAR0, existing registers */
45 /* Read from a direct address offset from BAR0, additional registers */
49 /* Write to a direct address offset from BAR0, additional registers */
/linux/samples/rust/
H A Drust_driver_pci.rs19 type Bar0 = pci::Bar<{ Regs::END }>; typedef
32 bar: Devres<Bar0>,
47 fn testdev(index: &TestIndex, bar: &Bar0) -> Result<u32> { in testdev()
/linux/drivers/infiniband/hw/usnic/
H A Dusnic_vnic.c97 struct vnic_dev_bar *bar0; in usnic_vnic_dump() local
101 bar0 = usnic_vnic_get_bar(vnic, 0); in usnic_vnic_dump()
103 "VF:%hu BAR0 bus_addr=%pa vaddr=0x%p size=%ld ", in usnic_vnic_dump()
105 &bar0->bus_addr, in usnic_vnic_dump()
106 bar0->vaddr, bar0->len); in usnic_vnic_dump()
/linux/arch/x86/kernel/
H A Dearly_printk.c267 u32 classcode, bar0; in early_pci_serial_init() local
309 bar0 = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0); in early_pci_serial_init()
324 if ((bar0 & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { in early_pci_serial_init()
326 early_serial_base = bar0 & PCI_BASE_ADDRESS_IO_MASK; in early_pci_serial_init()
335 (unsigned long)early_ioremap(bar0 & PCI_BASE_ADDRESS_MEM_MASK, 0x10); in early_pci_serial_init()
337 kexec_debug_8250_mmio32 = bar0 & PCI_BASE_ADDRESS_MEM_MASK; in early_pci_serial_init()
/linux/Documentation/ABI/testing/
H A Dconfigfs-spear-pcie-gadget29 bar0_address used to write and read bar0 mapped area in hex.
30 bar0_rw_offset used to write and read offset of bar0 where bar0_data
/linux/drivers/uio/
H A Duio_mf624.c22 /* BAR0 Interrupt control/status register */
152 /* Note: Datasheet says device uses BAR0, BAR1, BAR2 -- do not trust it */ in mf624_pci_probe()
154 /* BAR0 */ in mf624_pci_probe()
/linux/drivers/bluetooth/
H A Dhci_bcm4377.c486 * otp_offset: Offset to the start of the OTP inside BAR0
487 * bar0_window1: Backplane address mapped to the first window in BAR0
488 * bar0_window2: Backplane address mapped to the second window in BAR0
490 * second window in BAR0
540 * bar0: iomem pointing to BAR0
569 void __iomem *bar0; member
624 iowrite32(db, bcm4377->bar0 + BCM4377_BAR0_DOORBELL); in bcm4377_ring_doorbell()
949 bcm4377->bar0 + BCM4377_BAR0_SLEEP_CONTROL); in bcm4377_enqueue()
1865 iowrite32(0, bcm4377->bar0 + BCM4377_BAR0_HOST_WINDOW_LO); in bcm4377_boot()
1866 iowrite32(0, bcm4377->bar0 + BCM4377_BAR0_HOST_WINDOW_HI); in bcm4377_boot()
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp6000_pcie.c523 * BAR0.0: Reserved for General Mapping (for MSI-X access to PCIe SRAM)
524 * BAR0.1: Reserved for XPB access (for MSI-X access to PCIe PBA)
525 * BAR0.2: --
526 * BAR0.3: --
527 * BAR0.4: Reserved for Explicit 0.0-0.3 access
528 * BAR0.5: Reserved for Explicit 1.0-1.3 access
529 * BAR0.6: Reserved for Explicit 2.0-2.3 access
530 * BAR0.7: Reserved for Explicit 3.0-3.3 access
608 /* Configure, and lock, BAR0.0 for General Target use (MSI-X SRAM) */ in enable_bars()
660 /* Configure, and lock, BAR0.1 for PCIe XPB (MSI-X PBA) */ in enable_bars()
[all …]
/linux/drivers/pci/endpoint/functions/
H A Dpci-epf-ntb.c183 * | BAR0 | | | Doorbell 1 +-----------> MSI|X ADDRESS 1 |
329 *| BAR0 | | | Doorbell 1 +---+-------> MSI ADDRESS |
432 *| BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
710 *| BAR0 | | CONFIG REGION | | BAR0 |
755 *| BAR0 | | CONFIG REGION | | BAR0 |
826 * | BAR0 | | CONFIG REGION | | BAR0 |
840 * Clear BAR0 of EP CONTROLLER 1 which contains the HOST1's config and
841 * self scratchpad region (removes inbound ATU configuration). While BAR0 is
871 * | BAR0 | | CONFIG REGION | | BAR0 |
885 * Map BAR0 of EP CONTROLLER 1 which contains the HOST1's config and
[all …]
/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst239 BAR0 Config Region
261 BAR0 Config Region + Self Scratchpad
277 | BAR0 | | CONFIG REGION | | BAR0 |
293 region and scratchpad region (self scratchpad) using BAR0 of EP controller 1.
305 | BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
H A Dpci-test-howto.rst148 # RUN pci_ep_bar.BAR0.BAR_TEST ...
149 # OK pci_ep_bar.BAR0.BAR_TEST
150 ok 1 pci_ep_bar.BAR0.BAR_TEST
/linux/drivers/net/wireless/ath/ath9k/
H A Dath9k_pci_owl_loader.c46 u32 bar0; in ath9k_pci_fixup() local
73 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0); in ath9k_pci_fixup()
104 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, bar0); in ath9k_pci_fixup()
/linux/drivers/gpu/nova-core/
H A Dgfw.rs25 use crate::driver::Bar0;
43 pub(crate) fn wait_gfw_boot_completion(bar: &Bar0) -> Result { in wait_gfw_boot_completion()

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