Lines Matching full:bar0
1010 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_verify_pci_mode() local
1014 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1044 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_print_pci_mode() local
1050 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1114 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_tti() local
1138 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1163 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1168 writeq(val64, &bar0->tti_command_mem); in init_tti()
1170 if (wait_for_cmd_complete(&bar0->tti_command_mem, in init_tti()
1190 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_nic() local
1213 writeq(val64, &bar0->sw_reset); in init_nic()
1215 val64 = readq(&bar0->sw_reset); in init_nic()
1220 writeq(val64, &bar0->sw_reset); in init_nic()
1222 val64 = readq(&bar0->sw_reset); in init_nic()
1229 val64 = readq(&bar0->adapter_status); in init_nic()
1239 add = &bar0->mac_cfg; in init_nic()
1240 val64 = readq(&bar0->mac_cfg); in init_nic()
1242 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1244 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1248 val64 = readq(&bar0->mac_int_mask); in init_nic()
1249 val64 = readq(&bar0->mc_int_mask); in init_nic()
1250 val64 = readq(&bar0->xgxs_int_mask); in init_nic()
1254 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in init_nic()
1259 &bar0->dtx_control, UF); in init_nic()
1267 &bar0->dtx_control, UF); in init_nic()
1268 val64 = readq(&bar0->dtx_control); in init_nic()
1275 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1276 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1277 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1278 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1293 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1298 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1303 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1308 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1323 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); in init_nic()
1325 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1327 &bar0->tx_fifo_partition_0, (unsigned long long)val64); in init_nic()
1333 val64 = readq(&bar0->tx_pa_cfg); in init_nic()
1338 writeq(val64, &bar0->tx_pa_cfg); in init_nic()
1347 writeq(val64, &bar0->rx_queue_priority); in init_nic()
1396 writeq(val64, &bar0->rx_queue_cfg); in init_nic()
1405 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1406 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1407 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1408 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1409 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1413 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1414 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1415 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1416 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1418 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1422 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1424 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1426 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1428 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1430 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1434 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1435 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1436 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1437 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1439 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1443 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1445 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1447 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1449 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1451 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1455 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1457 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1459 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1461 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1463 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1467 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1469 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1471 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1473 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1475 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1479 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1480 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1481 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1482 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1484 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1489 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1491 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1500 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1501 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1502 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1503 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1504 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1507 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1511 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1512 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1513 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1514 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1516 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1519 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1523 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1525 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1527 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1529 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1531 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1534 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1538 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1539 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1540 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1541 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1543 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1546 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1550 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1552 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1554 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1556 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1558 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1561 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1565 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1567 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1569 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1571 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1573 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1576 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1580 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1582 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1584 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1586 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1588 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1591 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1595 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1596 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1597 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1598 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1600 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1603 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1610 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1615 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1629 &bar0->rts_frm_len_n[i]); in init_nic()
1644 writeq(mac_control->stats_mem_phy, &bar0->stat_addr); in init_nic()
1648 writeq(val64, &bar0->stat_byte_cnt); in init_nic()
1657 writeq(val64, &bar0->mac_link_util); in init_nic()
1683 writeq(val64, &bar0->rti_data1_mem); in init_nic()
1693 writeq(val64, &bar0->rti_data2_mem); in init_nic()
1699 writeq(val64, &bar0->rti_command_mem); in init_nic()
1710 val64 = readq(&bar0->rti_command_mem); in init_nic()
1728 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); in init_nic()
1729 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); in init_nic()
1732 add = &bar0->mac_cfg; in init_nic()
1733 val64 = readq(&bar0->mac_cfg); in init_nic()
1735 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1737 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1739 val64 = readq(&bar0->mac_cfg); in init_nic()
1742 add = &bar0->mac_cfg; in init_nic()
1743 val64 = readq(&bar0->mac_cfg); in init_nic()
1746 writeq(val64, &bar0->mac_cfg); in init_nic()
1748 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1750 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1758 val64 = readq(&bar0->rmac_pause_cfg); in init_nic()
1761 writeq(val64, &bar0->rmac_pause_cfg); in init_nic()
1775 writeq(val64, &bar0->mc_pause_thresh_q0q3); in init_nic()
1783 writeq(val64, &bar0->mc_pause_thresh_q4q7); in init_nic()
1789 val64 = readq(&bar0->pic_control); in init_nic()
1791 writeq(val64, &bar0->pic_control); in init_nic()
1794 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout); in init_nic()
1795 writeq(0x0, &bar0->read_retry_delay); in init_nic()
1796 writeq(0x0, &bar0->write_retry_delay); in init_nic()
1806 writeq(val64, &bar0->misc_control); in init_nic()
1807 val64 = readq(&bar0->pic_control2); in init_nic()
1809 writeq(val64, &bar0->pic_control2); in init_nic()
1813 writeq(val64, &bar0->tmac_avg_ipg); in init_nic()
1853 struct XENA_dev_config __iomem *bar0 = nic->bar0; in en_dis_err_alarms() local
1857 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask); in en_dis_err_alarms()
1864 TXDMA_SM_INT, flag, &bar0->txdma_int_mask); in en_dis_err_alarms()
1869 &bar0->pfc_err_mask); in en_dis_err_alarms()
1873 TDA_PCIX_ERR, flag, &bar0->tda_err_mask); in en_dis_err_alarms()
1881 flag, &bar0->pcc_err_mask); in en_dis_err_alarms()
1884 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask); in en_dis_err_alarms()
1889 flag, &bar0->lso_err_mask); in en_dis_err_alarms()
1892 flag, &bar0->tpa_err_mask); in en_dis_err_alarms()
1894 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask); in en_dis_err_alarms()
1900 &bar0->mac_int_mask); in en_dis_err_alarms()
1904 flag, &bar0->mac_tmac_err_mask); in en_dis_err_alarms()
1910 &bar0->xgxs_int_mask); in en_dis_err_alarms()
1913 flag, &bar0->xgxs_txgxs_err_mask); in en_dis_err_alarms()
1920 flag, &bar0->rxdma_int_mask); in en_dis_err_alarms()
1924 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask); in en_dis_err_alarms()
1928 &bar0->prc_pcix_err_mask); in en_dis_err_alarms()
1931 &bar0->rpa_err_mask); in en_dis_err_alarms()
1937 flag, &bar0->rda_err_mask); in en_dis_err_alarms()
1940 flag, &bar0->rti_err_mask); in en_dis_err_alarms()
1946 &bar0->mac_int_mask); in en_dis_err_alarms()
1953 flag, &bar0->mac_rmac_err_mask); in en_dis_err_alarms()
1959 &bar0->xgxs_int_mask); in en_dis_err_alarms()
1961 &bar0->xgxs_rxgxs_err_mask); in en_dis_err_alarms()
1967 flag, &bar0->mc_int_mask); in en_dis_err_alarms()
1970 &bar0->mc_err_mask); in en_dis_err_alarms()
1991 struct XENA_dev_config __iomem *bar0 = nic->bar0; in en_dis_able_nic_intrs() local
2011 &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2013 &bar0->gpio_int_mask); in en_dis_able_nic_intrs()
2015 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2021 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2033 writeq(0x0, &bar0->tx_traffic_mask); in en_dis_able_nic_intrs()
2039 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); in en_dis_able_nic_intrs()
2048 writeq(0x0, &bar0->rx_traffic_mask); in en_dis_able_nic_intrs()
2054 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); in en_dis_able_nic_intrs()
2058 temp64 = readq(&bar0->general_int_mask); in en_dis_able_nic_intrs()
2063 writeq(temp64, &bar0->general_int_mask); in en_dis_able_nic_intrs()
2065 nic->general_int_mask = readq(&bar0->general_int_mask); in en_dis_able_nic_intrs()
2079 struct XENA_dev_config __iomem *bar0 = sp->bar0; in verify_pcc_quiescent() local
2080 u64 val64 = readq(&bar0->adapter_status); in verify_pcc_quiescent()
2121 struct XENA_dev_config __iomem *bar0 = sp->bar0; in verify_xena_quiescence() local
2122 u64 val64 = readq(&bar0->adapter_status); in verify_xena_quiescence()
2187 struct XENA_dev_config __iomem *bar0 = sp->bar0; in fix_mac_address() local
2191 writeq(fix_mac[i++], &bar0->gpio_control); in fix_mac_address()
2193 (void) readq(&bar0->gpio_control); in fix_mac_address()
2212 struct XENA_dev_config __iomem *bar0 = nic->bar0; in start_nic() local
2224 &bar0->prc_rxd0_n[i]); in start_nic()
2226 val64 = readq(&bar0->prc_ctrl_n[i]); in start_nic()
2235 writeq(val64, &bar0->prc_ctrl_n[i]); in start_nic()
2240 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2242 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2246 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2248 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2257 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2259 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in start_nic()
2260 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2265 val64 = readq(&bar0->adapter_control); in start_nic()
2267 writeq(val64, &bar0->adapter_control); in start_nic()
2273 val64 = readq(&bar0->adapter_status); in start_nic()
2290 val64 = readq(&bar0->adapter_control); in start_nic()
2292 writeq(val64, &bar0->adapter_control); in start_nic()
2305 val64 = readq(&bar0->gpio_control); in start_nic()
2307 writeq(val64, &bar0->gpio_control); in start_nic()
2309 writeq(val64, (void __iomem *)bar0 + 0x2700); in start_nic()
2415 struct XENA_dev_config __iomem *bar0 = nic->bar0; in stop_nic() local
2426 val64 = readq(&bar0->adapter_control); in stop_nic()
2428 writeq(val64, &bar0->adapter_control); in stop_nic()
2769 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_poll_msix() local
2781 addr = (u8 __iomem *)&bar0->xmsi_mask_reg; in s2io_poll_msix()
2795 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_poll_inta() local
2815 writeq(0, &bar0->rx_traffic_mask); in s2io_poll_inta()
2816 readl(&bar0->rx_traffic_mask); in s2io_poll_inta()
2835 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_netpoll() local
2846 writeq(val64, &bar0->rx_traffic_int); in s2io_netpoll()
2847 writeq(val64, &bar0->tx_traffic_int); in s2io_netpoll()
3091 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_mdio_write() local
3097 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3099 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3108 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3110 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3117 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3119 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3137 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_mdio_read() local
3143 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3145 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3153 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3155 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3159 rval64 = readq(&bar0->mdio_control); in s2io_mdio_read()
3403 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_reset() local
3420 writeq(val64, &bar0->sw_reset); in s2io_reset()
3460 writeq(s2BIT(62), &bar0->txpic_int_reg); in s2io_reset()
3495 val64 = readq(&bar0->gpio_control); in s2io_reset()
3497 writeq(val64, &bar0->gpio_control); in s2io_reset()
3499 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_reset()
3507 val64 = readq(&bar0->pcc_err_reg); in s2io_reset()
3508 writeq(val64, &bar0->pcc_err_reg); in s2io_reset()
3527 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_swapper() local
3535 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3546 writeq(value[i], &bar0->swapper_ctrl); in s2io_set_swapper()
3547 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3560 valr = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3564 writeq(valt, &bar0->xmsi_address); in s2io_set_swapper()
3565 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3577 writeq((value[i] | valr), &bar0->swapper_ctrl); in s2io_set_swapper()
3578 writeq(valt, &bar0->xmsi_address); in s2io_set_swapper()
3579 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3591 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3612 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3636 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3638 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3644 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3658 struct XENA_dev_config __iomem *bar0 = nic->bar0; in wait_for_msix_trans() local
3663 val64 = readq(&bar0->xmsi_access); in wait_for_msix_trans()
3679 struct XENA_dev_config __iomem *bar0 = nic->bar0; in restore_xmsi_data() local
3688 writeq(nic->msix_info[i].addr, &bar0->xmsi_address); in restore_xmsi_data()
3689 writeq(nic->msix_info[i].data, &bar0->xmsi_data); in restore_xmsi_data()
3691 writeq(val64, &bar0->xmsi_access); in restore_xmsi_data()
3700 struct XENA_dev_config __iomem *bar0 = nic->bar0; in store_xmsi_data() local
3711 writeq(val64, &bar0->xmsi_access); in store_xmsi_data()
3717 addr = readq(&bar0->xmsi_address); in store_xmsi_data()
3718 data = readq(&bar0->xmsi_data); in store_xmsi_data()
3728 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_enable_msi_x() local
3772 rx_mat = readq(&bar0->rx_mat); in s2io_enable_msi_x()
3780 writeq(rx_mat, &bar0->rx_mat); in s2io_enable_msi_x()
3781 readq(&bar0->rx_mat); in s2io_enable_msi_x()
3825 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_test_msi() local
3840 saved64 = val64 = readq(&bar0->scheduled_int_ctrl); in s2io_test_msi()
3844 writeq(val64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
3859 writeq(saved64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
4209 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_msix_ring_handle() local
4218 addr = (u8 __iomem *)&bar0->xmsi_mask_reg; in s2io_msix_ring_handle()
4237 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_msix_fifo_handle() local
4244 reason = readq(&bar0->general_int_status); in s2io_msix_fifo_handle()
4250 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); in s2io_msix_fifo_handle()
4256 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); in s2io_msix_fifo_handle()
4261 writeq(sp->general_int_mask, &bar0->general_int_mask); in s2io_msix_fifo_handle()
4262 readl(&bar0->general_int_status); in s2io_msix_fifo_handle()
4271 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_txpic_intr_handle() local
4274 val64 = readq(&bar0->pic_int_status); in s2io_txpic_intr_handle()
4276 val64 = readq(&bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4285 writeq(val64, &bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4286 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4289 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4291 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4293 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4295 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4297 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4306 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4309 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4312 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4315 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4318 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4321 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4323 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4326 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4365 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_handle_errors() local
4393 val64 = readq(&bar0->mac_rmac_err_reg); in s2io_handle_errors()
4394 writeq(val64, &bar0->mac_rmac_err_reg); in s2io_handle_errors()
4400 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source, in s2io_handle_errors()
4405 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg, in s2io_handle_errors()
4411 val64 = readq(&bar0->ring_bump_counter1); in s2io_handle_errors()
4418 val64 = readq(&bar0->ring_bump_counter2); in s2io_handle_errors()
4426 val64 = readq(&bar0->txdma_int_status); in s2io_handle_errors()
4432 &bar0->pfc_err_reg, in s2io_handle_errors()
4436 &bar0->pfc_err_reg, in s2io_handle_errors()
4445 &bar0->tda_err_reg, in s2io_handle_errors()
4449 &bar0->tda_err_reg, in s2io_handle_errors()
4459 &bar0->pcc_err_reg, in s2io_handle_errors()
4463 &bar0->pcc_err_reg, in s2io_handle_errors()
4470 &bar0->tti_err_reg, in s2io_handle_errors()
4474 &bar0->tti_err_reg, in s2io_handle_errors()
4482 &bar0->lso_err_reg, in s2io_handle_errors()
4486 &bar0->lso_err_reg, in s2io_handle_errors()
4493 &bar0->tpa_err_reg, in s2io_handle_errors()
4497 &bar0->tpa_err_reg, in s2io_handle_errors()
4504 &bar0->sm_err_reg, in s2io_handle_errors()
4509 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4512 &bar0->mac_tmac_err_reg, in s2io_handle_errors()
4518 &bar0->mac_tmac_err_reg, in s2io_handle_errors()
4522 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4525 &bar0->xgxs_txgxs_err_reg, in s2io_handle_errors()
4529 &bar0->xgxs_txgxs_err_reg, in s2io_handle_errors()
4533 val64 = readq(&bar0->rxdma_int_status); in s2io_handle_errors()
4539 &bar0->rc_err_reg, in s2io_handle_errors()
4544 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg, in s2io_handle_errors()
4549 &bar0->prc_pcix_err_reg, in s2io_handle_errors()
4555 &bar0->prc_pcix_err_reg, in s2io_handle_errors()
4561 &bar0->rpa_err_reg, in s2io_handle_errors()
4565 &bar0->rpa_err_reg, in s2io_handle_errors()
4575 &bar0->rda_err_reg, in s2io_handle_errors()
4582 &bar0->rda_err_reg, in s2io_handle_errors()
4588 &bar0->rti_err_reg, in s2io_handle_errors()
4592 &bar0->rti_err_reg, in s2io_handle_errors()
4596 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4599 &bar0->mac_rmac_err_reg, in s2io_handle_errors()
4605 &bar0->mac_rmac_err_reg, in s2io_handle_errors()
4609 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4612 &bar0->xgxs_rxgxs_err_reg, in s2io_handle_errors()
4617 val64 = readq(&bar0->mc_int_status); in s2io_handle_errors()
4620 &bar0->mc_err_reg, in s2io_handle_errors()
4626 writeq(val64, &bar0->mc_err_reg); in s2io_handle_errors()
4667 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_isr() local
4690 reason = readq(&bar0->general_int_status); in s2io_isr()
4697 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); in s2io_isr()
4702 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask); in s2io_isr()
4703 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); in s2io_isr()
4704 readl(&bar0->rx_traffic_int); in s2io_isr()
4713 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); in s2io_isr()
4728 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); in s2io_isr()
4746 writeq(sp->general_int_mask, &bar0->general_int_mask); in s2io_isr()
4747 readl(&bar0->general_int_status); in s2io_isr()
4764 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_updt_stats() local
4772 writeq(val64, &bar0->stat_cfg); in s2io_updt_stats()
4775 val64 = readq(&bar0->stat_cfg); in s2io_updt_stats()
4892 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_multicast() local
4902 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4904 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
4908 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4910 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
4919 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4921 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
4925 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4927 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
4937 add = &bar0->mac_cfg; in s2io_set_multicast()
4938 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4941 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4943 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4947 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4949 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4953 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4959 add = &bar0->mac_cfg; in s2io_set_multicast()
4960 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4963 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4965 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4969 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4971 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4975 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4997 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4999 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
5004 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5007 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
5027 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
5029 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
5034 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5037 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
5127 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_add_mac() local
5130 &bar0->rmac_addr_data0_mem); in do_s2io_add_mac()
5134 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_add_mac()
5137 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in do_s2io_add_mac()
5173 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_read_unicast_mc() local
5178 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_read_unicast_mc()
5181 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in do_s2io_read_unicast_mc()
5187 tmp64 = readq(&bar0->rmac_addr_data0_mem); in do_s2io_read_unicast_mc()
5375 reg = readq(sp->bar0 + i); in s2io_ethtool_gregs()
5385 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_led() local
5391 val64 = readq(&bar0->gpio_control); in s2io_set_led()
5397 writeq(val64, &bar0->gpio_control); in s2io_set_led()
5399 val64 = readq(&bar0->adapter_control); in s2io_set_led()
5405 writeq(val64, &bar0->adapter_control); in s2io_set_led()
5426 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_set_led() local
5430 u64 val64 = readq(&bar0->adapter_control); in s2io_ethtool_set_led()
5439 sp->adapt_ctrl_org = readq(&bar0->gpio_control); in s2io_ethtool_set_led()
5452 writeq(sp->adapt_ctrl_org, &bar0->gpio_control); in s2io_ethtool_set_led()
5502 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_getpause_data() local
5504 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_getpause_data()
5528 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_setpause_data() local
5530 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5539 writeq(val64, &bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5564 struct XENA_dev_config __iomem *bar0 = sp->bar0; in read_eeprom() local
5572 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in read_eeprom()
5575 val64 = readq(&bar0->i2c_control); in read_eeprom()
5590 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5592 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5594 val64 = readq(&bar0->spi_control); in read_eeprom()
5599 *data = readq(&bar0->spi_data); in read_eeprom()
5630 struct XENA_dev_config __iomem *bar0 = sp->bar0; in write_eeprom() local
5638 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in write_eeprom()
5641 val64 = readq(&bar0->i2c_control); in write_eeprom()
5654 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data); in write_eeprom()
5659 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5661 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5663 val64 = readq(&bar0->spi_control); in write_eeprom()
5849 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_register_test() local
5853 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_register_test()
5859 val64 = readq(&bar0->rmac_pause_cfg); in s2io_register_test()
5865 val64 = readq(&bar0->rx_queue_cfg); in s2io_register_test()
5875 val64 = readq(&bar0->xgxs_efifo_cfg); in s2io_register_test()
5882 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5883 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5890 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5891 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
6054 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_link_test() local
6057 val64 = readq(&bar0->adapter_status); in s2io_link_test()
6081 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_rldram_test() local
6085 val64 = readq(&bar0->adapter_control); in s2io_rldram_test()
6087 writeq(val64, &bar0->adapter_control); in s2io_rldram_test()
6089 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6091 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6093 val64 = readq(&bar0->mc_rldram_mrs); in s2io_rldram_test()
6095 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6098 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6104 writeq(val64, &bar0->mc_rldram_test_d0); in s2io_rldram_test()
6109 writeq(val64, &bar0->mc_rldram_test_d1); in s2io_rldram_test()
6114 writeq(val64, &bar0->mc_rldram_test_d2); in s2io_rldram_test()
6117 writeq(val64, &bar0->mc_rldram_test_add); in s2io_rldram_test()
6122 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6125 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6135 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6138 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6147 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6157 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6652 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_change_mtu() local
6655 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in s2io_change_mtu()
6672 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_set_link() local
6695 val64 = readq(&bar0->adapter_status); in s2io_set_link()
6697 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) { in s2io_set_link()
6699 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6701 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6704 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6706 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6707 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6710 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6720 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6722 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6727 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6729 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6730 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6733 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6735 writeq(val64, &bar0->adapter_control); in s2io_set_link()
7014 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_card_down() local
7059 val64 = readq(&bar0->adapter_status); in do_s2io_card_down()
7608 struct XENA_dev_config __iomem *bar0 = nic->bar0; in rts_ds_steer() local
7615 writeq(val64, &bar0->rts_ds_mem_data); in rts_ds_steer()
7621 writeq(val64, &bar0->rts_ds_mem_ctrl); in rts_ds_steer()
7623 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl, in rts_ds_steer()
7667 struct XENA_dev_config __iomem *bar0 = NULL; in s2io_init_nic() local
7836 sp->bar0 = pci_ioremap_bar(pdev, 0); in s2io_init_nic()
7837 if (!sp->bar0) { in s2io_init_nic()
7932 bar0 = sp->bar0; in s2io_init_nic()
7935 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_init_nic()
7936 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_init_nic()
7939 tmp64 = readq(&bar0->rmac_addr_data0_mem); in s2io_init_nic()
8001 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8003 writeq(val64, &bar0->gpio_control); in s2io_init_nic()
8005 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_init_nic()
8006 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8118 iounmap(sp->bar0); in s2io_init_nic()
8156 iounmap(sp->bar0); in s2io_rem_nic()