1 // SPDX-License-Identifier: GPL-2.0
2
3 //! GPU Firmware (`GFW`) support, a.k.a `devinit`.
4 //!
5 //! Upon reset, the GPU runs some firmware code from the BIOS to setup its core parameters. Most of
6 //! the GPU is considered unusable until this step is completed, so we must wait on it before
7 //! performing driver initialization.
8 //!
9 //! A clarification about devinit terminology: devinit is a sequence of register read/writes after
10 //! reset that performs tasks such as:
11 //! 1. Programming VRAM memory controller timings.
12 //! 2. Power sequencing.
13 //! 3. Clock and PLL configuration.
14 //! 4. Thermal management.
15 //!
16 //! devinit itself is a 'script' which is interpreted by an interpreter program typically running
17 //! on the PMU microcontroller.
18 //!
19 //! Note that the devinit sequence also needs to run during suspend/resume.
20
21 use kernel::bindings;
22 use kernel::prelude::*;
23 use kernel::time::Delta;
24
25 use crate::driver::Bar0;
26 use crate::regs;
27 use crate::util;
28
29 /// Wait for the `GFW` (GPU firmware) boot completion signal (`GFW_BOOT`), or a 4 seconds timeout.
30 ///
31 /// Upon GPU reset, several microcontrollers (such as PMU, SEC2, GSP etc) run some firmware code to
32 /// setup its core parameters. Most of the GPU is considered unusable until this step is completed,
33 /// so it must be waited on very early during driver initialization.
34 ///
35 /// The `GFW` code includes several components that need to execute before the driver loads. These
36 /// components are located in the VBIOS ROM and executed in a sequence on these different
37 /// microcontrollers. The devinit sequence typically runs on the PMU, and the FWSEC runs on the
38 /// GSP.
39 ///
40 /// This function waits for a signal indicating that core initialization is complete. Before this
41 /// signal is received, little can be done with the GPU. This signal is set by the FWSEC running on
42 /// the GSP in Heavy-secured mode.
wait_gfw_boot_completion(bar: &Bar0) -> Result43 pub(crate) fn wait_gfw_boot_completion(bar: &Bar0) -> Result {
44 // Before accessing the completion status in `NV_PGC6_AON_SECURE_SCRATCH_GROUP_05`, we must
45 // first check `NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK`. This is because
46 // `NV_PGC6_AON_SECURE_SCRATCH_GROUP_05` becomes accessible only after the secure firmware
47 // (FWSEC) lowers the privilege level to allow CPU (LS/Light-secured) access. We can only
48 // safely read the status register from CPU (LS/Light-secured) once the mask indicates
49 // that the privilege level has been lowered.
50 //
51 // TIMEOUT: arbitrarily large value. GFW starts running immediately after the GPU is put out of
52 // reset, and should complete in less time than that.
53 util::wait_on(Delta::from_secs(4), || {
54 // Check that FWSEC has lowered its protection level before reading the GFW_BOOT status.
55 let gfw_booted = regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK::read(bar)
56 .read_protection_level0()
57 && regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT::read(bar).completed();
58
59 if gfw_booted {
60 Some(())
61 } else {
62 // TODO[DLAY]: replace with [1] once it merges.
63 // [1] https://lore.kernel.org/rust-for-linux/20250423192857.199712-6-fujita.tomonori@gmail.com/
64 //
65 // SAFETY: `msleep()` is safe to call with any parameter.
66 unsafe { bindings::msleep(1) };
67
68 None
69 }
70 })
71 }
72