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/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json581 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
586 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
600 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
605 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
610 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
615 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
620 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
625 "PublicDescription": "RD_CAS Access t
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/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json543 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
548 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
553 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
558 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
562 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
567 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
572 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
577 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
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/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json572 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
577 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
601 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
606 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
611 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
616 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
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/linux/Documentation/devicetree/bindings/access-controllers/
H A Daccess-controllers.yaml4 $id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml#
7 title: Generic Domain Access Controllers
13 Common access controllers properties
15 Access controllers are in charge of stating which of the hardware blocks under
18 or a group of hardware blocks. An access controller's domain is the set of
19 resources covered by the access controller.
21 This device tree binding can be used to bind devices to their access
22 controller provided by access-controllers property. In this case, the device
23 is a consumer and the access controller is the provider.
25 An access controller can be represented by any node in the device tree and
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/linux/Documentation/admin-guide/LSM/
H A DSmack.rst9 Smack is the Simplified Mandatory Access Control Kernel.
10 Smack is a kernel based implementation of mandatory access
13 Smack is not the only Mandatory Access Control scheme
14 available for Linux. Those new to Mandatory Access Control
33 access to systems that use them as Smack does.
50 load the Smack access rules
53 report if a process with one label has access
85 Used to make access control decisions. In almost all cases
95 label does not allow all of the access permitted to a process
102 the Smack rule (more below) that permitted the write access
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/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json8 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
52 … the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
102 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
122 …"PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a …
142 …"PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due…
643 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
653 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
662 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
672 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
682 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
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/linux/drivers/iommu/iommufd/
H A Ddevice.c1068 * a valid cur_ioas (access->ioas). A caller passing in a valid new_ioas should
1071 static int iommufd_access_change_ioas(struct iommufd_access *access, in iommufd_access_change_ioas() argument
1074 u32 iopt_access_list_id = access->iopt_access_list_id; in iommufd_access_change_ioas()
1075 struct iommufd_ioas *cur_ioas = access->ioas; in iommufd_access_change_ioas()
1078 lockdep_assert_held(&access->ioas_lock); in iommufd_access_change_ioas()
1081 if (cur_ioas != access->ioas_unpin) in iommufd_access_change_ioas()
1089 * iommufd_access_unpin_pages() can continue using access->ioas_unpin. in iommufd_access_change_ioas()
1091 access->ioas = NULL; in iommufd_access_change_ioas()
1094 rc = iopt_add_access(&new_ioas->iopt, access); in iommufd_access_change_ioas()
1096 access->ioas = cur_ioas; in iommufd_access_change_ioas()
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/linux/security/landlock/
H A Daudit.c15 #include "access.h"
89 const access_mask_t access) in log_blockers() argument
91 const unsigned long access_mask = access; in log_blockers()
95 for_each_set_bit(access_bit, &access_mask, BITS_PER_TYPE(access)) { in log_blockers()
188 for (ssize_t i = ARRAY_SIZE(masks->access) - 1; i >= 0; i--) { in get_denied_layer()
189 if (masks->access[i] & *access_request) { in get_denied_layer()
190 *access_request &= masks->access[i]; in get_denied_layer()
208 .access[0] = LANDLOCK_ACCESS_FS_EXECUTE | in test_get_denied_layer()
210 .access[1] = LANDLOCK_ACCESS_FS_READ_FILE | in test_get_denied_layer()
212 .access[2] = LANDLOCK_ACCESS_FS_REMOVE_DIR, in test_get_denied_layer()
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H A Druleset.c25 #include "access.h"
200 * access rights.
204 * access rights.
249 * Extends access rights when the request comes from in insert_rule()
256 this->layers[0].access |= (*layers)[0].access; in insert_rule()
264 * Intersects access rights when it is a merge between a in insert_rule()
293 .access = ~0, in build_check_layer()
297 * Checks that .level and .access are large enough to contain their expected in build_check_layer()
301 BUILD_BUG_ON(layer.access < LANDLOCK_MASK_ACCESS_FS); in build_check_layer()
307 const access_mask_t access) in landlock_insert_rule() argument
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H A Dfs.c42 #include "access.h"
206 /* Other commands are guarded by the access right. */ in is_masked_device_ioctl()
310 /* All access rights that can be tied to files. */
332 /* Files only get access rights that make sense. */ in landlock_append_fs_rule()
339 /* Transforms relative access rights to absolute ones. */ in landlock_append_fs_rule()
356 /* Access-control management */
386 * Allows access to pseudo filesystems that will never be mountable (e.g.
402 * Returns true iff the child file with the given src_child access rights under
403 * src_parent would result in having the same or fewer access rights if it were
411 for (size_t i = 0; i < ARRAY_SIZE(new_parent->access); i++) { in may_refer()
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/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json8 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
52 … the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
102 …"PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per …
122 …"PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a …
142 …"PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due…
1019 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
1029 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
1038 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
1048 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
1058 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
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/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A Dl3_cache.json4 …"BriefDescription": "This event counts operations that cause a cache access to the L3 cache, as de…
8 …"BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation…
13 … "BriefDescription": "This event counts operations that cause a cache access to the L3 cache."
18 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand access."
23 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand read access."
28 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand write access."
48 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand access."
53 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand read access."
58 … "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand write access."
78 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand access."
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H A Dtlb.json12 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D TLB. See L1D_…
16 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I TLB. See L1I_…
24 …"BriefDescription": "This event counts operations that cause a TLB access to the L2D TLB. See L2D_…
28 … "BriefDescription": "This event counts data TLB access with at least one translation table walk."
32 …"BriefDescription": "This event counts instruction TLB access with at least one translation table …
37 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 4KB page."
42 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 64KB page."
47 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 2MB page."
52 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 32MB page."
57 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 512MB page…
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H A Dl1d_cache.json8 …"BriefDescription": "This event counts operations that cause a cache access to the L1D cache. See …
20 "BriefDescription": "This event counts L1D CACHE caused by read access."
24 "BriefDescription": "This event counts L1D CACHE caused by write access."
28 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by read access."
32 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by write access."
37 "BriefDescription": "This event counts L1D_CACHE caused by demand access."
42 "BriefDescription": "This event counts L1D_CACHE caused by demand read access."
47 "BriefDescription": "This event counts L1D_CACHE caused by demand write access."
52 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access."
57 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand read access."
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H A Dl2_cache.json4 …"BriefDescription": "This event counts operations that cause a cache access to the L2 cache. See L…
20 …"BriefDescription": "This event counts operations that cause a TLB access to the L2I TLB. See L2I_…
24 "BriefDescription": "This event counts L2D_CACHE caused by read access."
28 "BriefDescription": "This event counts L2D_CACHE caused by write access."
32 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by read access."
36 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by write access."
45 "BriefDescription": "This event counts L2D_CACHE caused by demand access."
50 "BriefDescription": "This event counts L2D_CACHE caused by demand read access."
55 "BriefDescription": "This event counts L2D_CACHE caused by demand write access."
65 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access."
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h123 * @reg: FAU atomic register to access. 0 <= reg < 2048.
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
143 * @reg: FAU atomic register to access. 0 <= reg < 2048.
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
146 * - Step by 8 for 64 bit access.
148 * Note: When performing 32 and 64 bit access, only the low
164 * @reg: FAU atomic register to access. 0 <= reg < 2048.
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/linux/tools/testing/selftests/bpf/verifier/
H A Ddirect_value_access.c2 "direct map access, write test 1",
14 "direct map access, write test 2",
26 "direct map access, write test 3",
38 "direct map access, write test 4",
50 "direct map access, write test 5",
62 "direct map access, write test 6",
75 "direct map access, write test 7",
84 .errstr = "invalid access to map value pointer, value_size=48 off=4294967295",
87 "direct map access, write test 8",
99 "direct map access, writ
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H A Dctx_skb.c2 "access skb fields ok",
33 "access skb fields bad1",
38 .errstr = "invalid bpf_context access",
42 "access skb fields bad2",
63 "access skb fields bad3",
85 "access skb fields bad4",
108 "invalid access __sk_buff family",
114 .errstr = "invalid bpf_context access",
118 "invalid access __sk_buff remote_ip4",
124 .errstr = "invalid bpf_context access",
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/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A Duncore-cache.json3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
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/linux/include/linux/
H A Dkcsan-checks.h3 * KCSAN access checks and modifiers. These can be used to explicitly check
16 /* Access types -- if KCSAN_ACCESS_WRITE is not set, the access is a read. */
17 #define KCSAN_ACCESS_WRITE (1 << 0) /* Access is a write. */
19 #define KCSAN_ACCESS_ATOMIC (1 << 2) /* Access is atomic. */
21 #define KCSAN_ACCESS_ASSERT (1 << 3) /* Access is an assertion. */
22 #define KCSAN_ACCESS_SCOPED (1 << 4) /* Access is a scoped access. */
27 * to validate access to an address. Never use these in header files!
31 * __kcsan_check_access - check generic access for races
33 * @ptr: address of access
34 * @size: size of access
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/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Duncore-cache.json3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
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/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-memory.json542 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
551 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
560 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
569 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
578 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
587 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
596 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
605 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
614 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
623 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
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/linux/Documentation/core-api/
H A Dunaligned-memory-access.rst14 when it comes to memory access. This document presents some details about
19 The definition of an unaligned access
26 access.
28 The above may seem a little vague, as memory access can happen in different
32 which will compile to multiple-byte memory access instructions, namely when
47 of memory access. However, we must consider ALL supported architectures;
52 Why unaligned access is bad
55 The effects of performing an unaligned memory access vary from architecture
62 happen. The exception handler is able to correct the unaligned access,
66 unaligned access to be corrected.
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/linux/Documentation/admin-guide/mm/damon/
H A Dstart.rst37 Snapshot Data Access Patterns
40 The commands below show the memory access pattern of a program at the moment of
45 $ sudo damo report access
48 0 addr 86.182 TiB size 8.000 KiB access 0 % age 14.900 s
49 1 addr 86.182 TiB size 8.000 KiB access 60 % age 0 ns
50 2 addr 86.182 TiB size 3.422 MiB access 0 % age 4.100 s
51 3 addr 86.182 TiB size 2.004 MiB access 95 % age 2.200 s
52 4 addr 86.182 TiB size 29.688 MiB access 0 % age 14.100 s
53 5 addr 86.182 TiB size 29.516 MiB access 0 % age 16.700 s
54 6 addr 86.182 TiB size 29.633 MiB access 0 % age 17.900 s
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/linux/tools/testing/selftests/bpf/progs/
H A Dverifier_helper_value_access.c42 __description("helper access to map: full range")
68 __description("helper access to map: partial range")
98 __description("helper access to map: empty range")
125 __description("helper access to map: possibly-empty ange")
154 __description("helper access to map: out-of-bound range")
155 __failure __msg("invalid access to map value, value_size=48 off=0 size=56")
180 __description("helper access to map: negative range")
205 __description("helper access to adjusted map (via const imm): full range")
233 __description("helper access to adjusted map (via const imm): partial range")
260 __description("helper access to adjusted map (via const imm): empty range")
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