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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.yaml35 enum: [ ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1,
102 atb {
103 nvidia,pins = "atb", "gma", "gme";
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-trimslice.dts49 atb {
50 nvidia,pins = "atb", "gma";
212 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
H A Dtegra20-tamonten.dtsi42 atb {
43 nvidia,pins = "atb", "gma", "gme";
185 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
H A Dtegra20-paz00.dts64 atb {
65 nvidia,pins = "atb", "gma", "gme";
201 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
H A Dtegra20-ventana.dts58 atb {
59 nvidia,pins = "atb", "gma", "gme";
208 nvidia,pins = "ata", "atb", "atc", "atd",
H A Dtegra20-harmony.dts56 atb {
57 nvidia,pins = "atb", "gma", "gme";
203 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
H A Dtegra20-seaboard.dts56 atb {
57 nvidia,pins = "atb", "gma", "gme";
206 nvidia,pins = "ata", "atb", "atc", "atd",
H A Dtegra20-acer-a500-picasso.dts99 atb {
100 nvidia,pins = "atb", "gma", "gme";
249 nvidia,pins = "ata", "atb", "atc", "atd",
H A Dtegra20-colibri.dtsi229 nvidia,pins = "atb", "gma";
/linux/arch/powerpc/boot/dts/fsl/
H A De500v1_power_isa.dtsi40 power-isa-atb; // Alternate Time Base
H A De500v2_power_isa.dtsi40 power-isa-atb; // Alternate Time Base
H A De500mc_power_isa.dtsi40 power-isa-atb; // Alternate Time Base
H A De5500_power_isa.dtsi40 power-isa-atb; // Alternate Time Base
H A De6500_power_isa.dtsi40 power-isa-atb; // Alternate Time Base
/linux/drivers/clk/
H A Dclk-npcm8xx.c365 hw = devm_clk_hw_register_fixed_factor(dev, "atb", "axi", 0, 1, 2); in npcm8xx_clk_probe()
367 return dev_err_probe(dev, PTR_ERR(hw), "Can't register atb div2\n"); in npcm8xx_clk_probe()
/linux/kernel/rcu/
H A Dtree_stall.h893 bool atb = false; in rcu_check_boost_fail() local
904 atb = true; in rcu_check_boost_fail()
911 atb = true; in rcu_check_boost_fail()
928 return atb; in rcu_check_boost_fail()
/linux/drivers/clk/samsung/
H A Dclk-cpu.c245 * In Exynos4210, ATB clock parent is also mout_core. So in exynos_cpuclk_pre_rate_change()
246 * ATB clock also needs to be maintained at safe speed. in exynos_cpuclk_pre_rate_change()
H A Dclk-exynos4.c1197 #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ argument
1198 (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h540 #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h540 #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h497 #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h561 #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
/linux/drivers/soc/samsung/
H A Dexynos5420-pmu.c238 * If L2_COMMON is turned off, clocks related to ATB async in exynos5420_pmu_init()
/linux/drivers/clk/mediatek/
H A Dclk-mt8196-topckgen.c672 MUX_CLR_SET_UPD(CLK_TOP_ATB, "atb",
/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_gpu.c1212 dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB ASYNC overflow\n"); in a5xx_rbbm_err_irq()
1215 dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB bus overflow\n"); in a5xx_rbbm_err_irq()

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