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/linux/arch/arm/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
14 - NEON (Advanced SIMD) extensions
17 tristate "Hash functions: GHASH (PMULL/NEON/ARMv8 Crypto Extensions)"
25 GCM GHASH function (NIST SP800-38D)
28 - PMULL (Polynomial Multiply Long) instructions
29 - NEON (Advanced SIMD) extensions
30 - ARMv8 Crypto Extensions
34 that is part of the ARMv8 Crypto Extensions, or a slower variant that
45 - NEON (Advanced SIMD) extensions
55 - NEON (Advanced SIMD) extensions
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H A Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Accelerated GHASH implementation with NEON/ARMv8 vmull.p8/64 instructions.
5 * Copyright (C) 2015 - 2017 Linaro Ltd.
12 .arch armv8-a
13 .fpu crypto-neon-fp-armv8
101 * This implementation of 64x64 -> 128 bit polynomial multiplication
102 * using vmull.p8 instructions (8x8 -> 16) is taken from the paper
105 * Ricardo Dahab (https://hal.inria.fr/hal-01506572)
107 * It has been slightly tweaked for in-order performance, and to allow
159 // PMULL (64x64->128) based reduction for CPUs that can do
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/linux/Documentation/trace/coresight/
H A Dcoresight-cpu-debug.rst9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
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/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 tristate "Arm NI-700 PMU support"
55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
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/linux/Documentation/devicetree/bindings/arm/nuvoton/
H A Dnuvoton,ma35d1.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton MA35 series SoC based platforms
10 - Jacky Huang <ychuang3@nuvoton.com>
13 Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
22 - description: MA35D1 based boards
24 - enum:
25 - nuvoton,ma35d1-iot
26 - nuvoton,ma35d1-som
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/linux/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
279 ARM 64-bit (AArch64) Linux support.
287 # required due to use of the -Zfixed-x18 flag.
290 # -Zsanitizer=shadow-call-stack flag.
300 depends on $(cc-option,-fpatchable-function-entry=2)
326 # VA_BITS - PAGE_SHIFT - 3
404 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
409 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
459 at stage-2.
467 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
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/linux/arch/arm64/crypto/
H A Dpolyval-ce-glue.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Glue code for POLYVAL using ARMv8 Crypto Extensions
5 * Copyright (c) 2007 Nokia Siemens Networks - Mikko Herranen <mh1@iki.fi>
12 * Glue code based on ghash-clmulni-intel_glue.c.
15 * ARMv8 Crypto Extensions instructions to implement the finite field operations.
56 polyval_update_non4k(keys->key_powers[NUM_KEY_POWERS-1], in, in internal_polyval_update()
79 return -EINVAL; in polyval_arm64_setkey()
81 memcpy(tctx->key_powers[NUM_KEY_POWERS-1], key, POLYVAL_BLOCK_SIZE); in polyval_arm64_setkey()
83 for (i = NUM_KEY_POWERS-2; i >= 0; i--) { in polyval_arm64_setkey()
84 memcpy(tctx->key_powers[i], key, POLYVAL_BLOCK_SIZE); in polyval_arm64_setkey()
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H A Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Accelerated GHASH implementation with ARMv8 PMULL instructions.
5 * Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
61 .arch armv8-a+crypto
149 ld1 {HH.2d-HH4.2d}, [x8]
197 // PMULL (64x64->128) based reduction for CPUs that can do
214 // 64x64->128 PMULL instruction
256 1: ld1 {XM3.16b-TT4.16b}, [x2], #64
388 ld1 {K0.4s-K3.4s}, [\rk]
389 ld1 {K4.4s-K5.4s}, [\tmp]
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H A Dpoly1305-armv8.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, initially for the OpenSSL
9 # This module implements Poly1305 hash for ARMv8.
15 # IALU/gcc-4.9 NEON
18 # Cortex-A53 2.69/+58% 1.47
19 # Cortex-A57 2.70/+7% 1.14
21 # X-Gene 2.13/+68% 2.27
26 # (*) estimate based on resources availability is less than 1.0,
35 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
36 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
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/linux/Documentation/devicetree/bindings/arm/
H A Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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H A Darm,coresight-cpu-debug.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight CPU debug component are compliant with the ARMv8 architecture
18 external debug module is mainly used for two modes: self-hosted debug and
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/linux/drivers/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
21 Support for NVIDIA Tegra AP20 and T20 processors, based on the
35 Support for NVIDIA Tegra T30 processor family, based on the
47 Support for NVIDIA Tegra T114 processor family, based on the
58 Support for NVIDIA Tegra T124 processor family, based on the
63 # 64-bit ARM SoCs
72 Enable support for NVIDIA Tegra132 SoC, based on the Denver
73 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
75 Tegra124's "4+1" Cortex-A15 CPU complex.
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/linux/Documentation/arch/arm64/
H A Dmemory-tagging-extension.rst8 Date: 2020-02-25
16 ARMv8.5 based processors introduce the Memory Tagging Extension (MTE)
17 feature. MTE is built on top of the ARMv8.0 virtual address tagging TBI
18 (Top Byte Ignore) feature and allows software to access a 4-bit
19 allocation tag for each 16-byte granule in the physical address space.
20 Such memory range must be mapped with the Normal-Tagged memory
21 attribute. A logical tag is derived from bits 59-56 of the virtual
34 --------
40 ``PROT_MTE`` - Pages allow access to the MTE allocation tags.
43 user address space and preserved on copy-on-write. ``MAP_SHARED`` is
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H A Dperf.rst1 .. SPDX-License-Identifier: GPL-2.0
13 :Date: 2019-03-06
16 ------------
24 --------------
39 ----------
46 For a non-VHE host this attribute will exclude EL2 as we consider the
55 ----------------------------
59 The KVM host may run at EL0 (userspace), EL1 (non-VHE kernel) and EL2 (VHE
60 kernel or non-VHE hypervisor).
65 exclusively rely on the PMU's hardware exception filtering - therefore we
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H A Dacpi_object_usage.rst16 - Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT
18 - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT
20 - Optional: AGDI, BGRT, CEDT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT,
24 - Not supported: AEST, APMT, BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT,
28 Table Usage for ARMv8 Linux
41 This table describes a non-maskable event, that is used by the platform
68 Optional, not currently supported, with no real use-case for an
83 time as ARM-compatible hardware is available, and the specification
151 UEFI-based; if it is UEFI-based, this table may be supplied. When this
167 the hardware reduced profile, and only 64-bit address fields will
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/linux/lib/
H A DKconfig.kasan1 # SPDX-License-Identifier: GPL-2.0-only
23 def_bool $(cc-option, -fsanitize=kernel-address)
26 def_bool $(cc-option, -fsanitize=kernel-hwaddress)
43 Enables KASAN (Kernel Address Sanitizer) - a dynamic memory safety
44 error detector designed to find out-of-bounds and use-after-free bugs.
46 See Documentation/dev-tools/kasan.rst for details.
53 …def_bool (CC_IS_CLANG && $(cc-option,-fsanitize=kernel-address -mllvm -asan-kernel-mem-intrinsic-p…
54 (CC_IS_GCC && $(cc-option,-fsanitize=kernel-address --param asan-kernel-mem-intrinsic-prefix=1))
69 2. Software Tag-Based KASAN (arm64 only, based on software memory
72 3. Hardware Tag-Based KASAN (arm64 only, based on hardware memory
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/linux/arch/arm64/kvm/hyp/
H A Dexception.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012,2013 - ARM Ltd
8 * Based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
63 vcpu->arch.ctxt.spsr_abt = val; in __vcpu_write_spsr_abt()
71 vcpu->arch.ctxt.spsr_und = val; in __vcpu_write_spsr_und()
77 * The EL passed to this function *must* be a non-secure, privileged mode with
85 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
86 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
134 if (kvm_has_mte(kern_hyp_va(vcpu->kvm))) in enter_exception64()
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-cpu-debug.c1 // SPDX-License-Identifier: GPL-2.0
29 #include "coresight-priv.h"
66 * NOTE: armv8 and armv7 have different definition for the register,
69 * 0b0000 - Sample offset applies based on the instruction state, we
71 * 0b0001 - No offset applies.
72 * 0b0010 - No offset applies, but do not use in AArch32 mode
118 writel_relaxed(0x0, drvdata->base + EDOSLAR); in debug_os_unlock()
130 * - CPU power domain is powered off;
131 * - The OS Double Lock is locked;
138 if (!(drvdata->edprsr & EDPRSR_PU)) in debug_access_permitted()
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/linux/Documentation/arch/arm/samsung/
H A Dbootloader-interface.rst10 and boot loaders on Samsung Exynos based boards. This is not a definition
14 In the document "boot loader" means any of following: U-boot, proprietary
15 SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before
19 1. Non-Secure mode
65 3. Other (regardless of secure/non-secure mode)
72 0x0908 Non-zero Secondary CPU boot up indicator
79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
81 MCPM - Multi-Cluster Power Management
/linux/Documentation/admin-guide/kdump/
H A Dvmcoreinfo.rst11 section and used by user-space tools like crash and makedumpfile to
18 ------------------------
25 ---------
32 -----------
39 User-space tools can get the kernel name, host name, kernel release
43 ---------------------
49 ---------------
56 --------------
62 ------
69 -------------
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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/linux/Documentation/arch/arm/
H A Dmarvell.rst13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
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/linux/drivers/clocksource/
H A Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include <linux/arm-smccc.h>
77 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
80 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
81 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
106 * Makes an educated guess at a valid counter width based on the Generic Timer
109 * 2) a roll-over time of not less than 40 years
118 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64); in arch_counter_get_width()
133 writel_relaxed((u32)val, timer->base + CNTP_CTL); in arch_timer_reg_write()
140 writeq_relaxed(val, timer->base + CNTP_CVAL_LO); in arch_timer_reg_write()
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g057.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_extal_clk: audio-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
24 * The default cluster table is based on the assumption that the PLLCA55 clock
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/linux/arch/arm/mm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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