Lines Matching +full:armv8 +full:- +full:based
1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 tristate "Arm NI-700 PMU support"
55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
63 Say y if you want to use CPU performance monitors on ARM-based
80 bool "RISC-V PMU framework"
83 Say y if you want to use CPU performance monitors on RISCV-based
90 bool "RISC-V legacy PMU implementation"
94 implementation on RISC-V based systems. This only allows counting
100 bool "RISC-V PMU based on SBI PMU extension"
104 using SBI PMU extension on RISC-V based systems. This option provides
127 non-standard behaviour via the regular SBI PMU driver and
144 based on the Stream ID of the corresponding master.
152 version 3. The PMUv3 is the CPU performance monitors on ARMv8
191 bool "Qualcomm Technologies L2-cache PMU"
201 bool "Qualcomm Technologies L3-cache PMU"
222 bool "APM X-Gene SoC PMU"
225 Say y if you want to use APM X-Gene SoC performance monitors.
228 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
231 Enable perf support for the ARMv8.2 Statistical Profiling
242 branch types and privilege based filtering. It captures additional
247 tristate "Enable PMU support for the ARM DMC-620 memory controller"
250 Support for PMU events monitoring on the ARM DMC-620 memory
254 tristate "Marvell CN10K LLC-TAD PMU"
257 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
264 Provides support for the non-architectural CPU PMUs present on
268 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
272 Sub-system.
303 monitoring units and provide standard perf based interfaces.