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/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,apll-clock.yaml4 $id: http://devicetree.org/schemas/clock/ti/ti,apll-clock.yaml#
7 title: Texas Instruments APLL clock
16 This binding assumes a register-mapped APLL with usually two selectable
20 power stop etc.) APLL mostly behaves like a subtype of a DPLL, although
26 - ti,dra7-apll-clock
27 - ti,omap2-apll-clock
41 Address and length of the register set for controlling the APLL.
75 compatible = "ti,dra7-apll-clock";
82 compatible = "ti,omap2-apll-clock";
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-afe-clk.h28 int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);
29 int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);
30 int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);
31 int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);
/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c26 static const char * const apll_sels[] = { "apll", "apll_pfd_sel", };
34 /* used by sosc/sirc/firc/ddr/spll/apll dividers */
80 …hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll", "apll_pre_div", base + 0x500… in imx7ulp_clk_scg1_init()
83 /* APLL PFDs */ in imx7ulp_clk_scg1_init()
84 …hws[IMX7ULP_CLK_APLL_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd0", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
85 …hws[IMX7ULP_CLK_APLL_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd1", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
86 …hws[IMX7ULP_CLK_APLL_PFD2] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd2", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
87 …hws[IMX7ULP_CLK_APLL_PFD3] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd3", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-dai-tdm.c22 unsigned int rate; /* for determine which apll to use */
222 /* which apll */ in mtk_afe_tdm_mclk_apll_connect()
253 /* which apll */ in mtk_afe_tdm_apll_connect()
256 /* choose APLL from tdm rate */ in mtk_afe_tdm_apll_connect()
339 int apll; in mtk_dai_tdm_cal_mclk() local
342 apll = mt8186_get_apll_by_rate(afe, freq); in mtk_dai_tdm_cal_mclk()
343 apll_rate = mt8186_get_apll_rate(afe, apll); in mtk_dai_tdm_cal_mclk()
353 "%s(), APLL cannot generate %d Hz", __func__, freq); in mtk_dai_tdm_cal_mclk()
358 tdm_priv->mclk_apll = apll; in mtk_dai_tdm_cal_mclk()
H A Dmt8186-dai-i2s.c43 int rate; /* for determine which apll to use */
508 /* apll */
586 /* which apll */ in mtk_afe_i2s_apll_connect()
588 /* choose APLL from i2s rate */ in mtk_afe_i2s_apll_connect()
627 /* which apll */ in mtk_afe_mclk_apll_connect()
1006 int apll; in mtk_dai_i2s_set_sysclk() local
1016 apll = mt8186_get_apll_by_rate(afe, freq); in mtk_dai_i2s_set_sysclk()
1017 apll_rate = mt8186_get_apll_rate(afe, apll); in mtk_dai_i2s_set_sysclk()
1020 dev_err(afe->dev, "%s(), freq > apll rate", __func__); in mtk_dai_i2s_set_sysclk()
1025 dev_err(afe->dev, "%s(), APLL canno in mtk_dai_i2s_set_sysclk()
[all...]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-afe-clk.c29 /* apll related mux */
230 /* apll */
384 /* setting for APLL */ in mt8183_apll1_enable()
438 /* setting for APLL */ in mt8183_apll2_enable()
487 int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll) in mt8183_get_apll_rate() argument
489 return (apll == MT8183_APLL1) ? 180633600 : 196608000; in mt8183_get_apll_rate()
545 int apll = mt8183_get_apll_by_rate(afe, rate); in mt8183_mck_enable() local
546 int apll_clk_id = apll == MT8183_APLL1 ? in mt8183_mck_enable()
556 /* select apll */ in mt8183_mck_enable()
H A Dmt8183-afe-clk.h12 /* APLL */
32 int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll);
H A Dmt8183-dai-tdm.c340 /* which apll */ in mtk_afe_tdm_apll_connect()
440 int apll; in mtk_dai_tdm_cal_mclk() local
443 apll = mt8183_get_apll_by_rate(afe, freq); in mtk_dai_tdm_cal_mclk()
444 apll_rate = mt8183_get_apll_rate(afe, apll); in mtk_dai_tdm_cal_mclk()
454 "%s(), APLL cannot generate %d Hz", __func__, freq); in mtk_dai_tdm_cal_mclk()
459 tdm_priv->mclk_apll = apll; in mtk_dai_tdm_cal_mclk()
/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-pcc-clock.yaml54 - description: apll pfd2
55 - description: apll pfd1
56 - description: apll pfd0
H A Dnuvoton,ma35d1-clk.yaml36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1.c89 { .fw_name = "apll", },
95 { .fw_name = "apll", },
294 { .fw_name = "apll", },
299 { .fw_name = "apll", },
304 { .fw_name = "apll", },
309 { .fw_name = "apll", },
314 { .fw_name = "apll", },
319 { .fw_name = "apll", },
323 { .fw_name = "apll", },
328 { .fw_name = "apll", },
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-rk3036.c21 apll, dpll, gpll, enumerator
117 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
118 PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
120 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
123 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
127 PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
138 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
H A Dclk-rv1108.c19 apll, dpll, gpll, enumerator
127 PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
147 PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" };
151 PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" };
154 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
203 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
537 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
666 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
H A Dclk-rk3328.c21 apll, dpll, cpll, gpll, npll, enumerator
147 PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
159 PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" };
215 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
286 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c290 /* setting for APLL */ in mt8192_apll1_enable()
340 /* setting for APLL */ in mt8192_apll2_enable()
385 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll) in mt8192_get_apll_rate() argument
387 return (apll == MT8192_APLL1) ? 180633600 : 196608000; in mt8192_get_apll_rate()
565 int apll = mt8192_get_apll_by_rate(afe, rate); in mt8192_mck_enable() local
566 int apll_clk_id = apll == MT8192_APLL1 ? in mt8192_mck_enable()
572 /* select apll */ in mt8192_mck_enable()
H A Dmt8192-afe-clk.h165 /* APLL */
186 /* apll related mux */
233 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll);
H A Dmt8192-dai-tdm.c388 /* which apll */ in mtk_afe_tdm_apll_connect()
489 int apll; in mtk_dai_tdm_cal_mclk() local
492 apll = mt8192_get_apll_by_rate(afe, freq); in mtk_dai_tdm_cal_mclk()
493 apll_rate = mt8192_get_apll_rate(afe, apll); in mtk_dai_tdm_cal_mclk()
503 "%s(), APLL cannot generate %d Hz", __func__, freq); in mtk_dai_tdm_cal_mclk()
508 tdm_priv->mclk_apll = apll; in mtk_dai_tdm_cal_mclk()
H A Dmt8192-dai-i2s.c45 int rate; /* for determine which apll to use */
882 /* apll */
982 /* which apll */ in mtk_afe_i2s_apll_connect()
985 /* choose APLL from i2s rate */ in mtk_afe_i2s_apll_connect()
1037 /* which apll */ in mtk_afe_mclk_apll_connect()
1779 int apll; in mtk_dai_i2s_set_sysclk() local
1794 apll = mt8192_get_apll_by_rate(afe, freq); in mtk_dai_i2s_set_sysclk()
1795 apll_rate = mt8192_get_apll_rate(afe, apll); in mtk_dai_i2s_set_sysclk()
1798 dev_warn(afe->dev, "%s(), freq > apll rate", __func__); in mtk_dai_i2s_set_sysclk()
1803 dev_warn(afe->dev, "%s(), APLL ca in mtk_dai_i2s_set_sysclk()
[all...]
/linux/drivers/clk/ti/
H A Dapll.c3 * OMAP APLL clock support
200 pr_err("dra7 apll %pOFn must have parent(s)\n", node); in of_dra7_apll_setup()
230 CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
409 CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
H A DMakefile6 fixed-factor.o mux.o apll.o \
/linux/drivers/clk/
H A Dclk-versaclock7.c45 /* APLL denominator is fixed at 2^27 */
118 * Changing the APLL frequency is currently not supported.
119 * The APLL will consist of an opaque block between the XO and FOD/IODs and
735 dev_err(&vc7->client->dev, "unable to read apll\n"); in vc7_get_apll_rate()
755 pr_debug("%s - refin_div: %llu, apll rate: %llu\n", in vc7_get_apll_rate()
1135 /* Register APLL */ in vc7_probe()
1144 "failed to register apll\n"); in vc7_probe()
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-afe-clk.c99 spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/
352 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll) in mt8195_afe_get_mclk_source_clk_id()
355 int clk_id = mt8195_afe_get_mclk_source_clk_id(apll); in mt8195_afe_get_mclk_source_clk_id()
358 mt8195_afe_get_mclk_source_rate(struct mtk_base_afe * afe,int apll) mt8195_afe_get_mclk_source_rate() argument
H A Dmt8195-afe-clk.h101 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
H A Dmt8195-dai-etdm.c1912 int apll; in mtk_dai_etdm_mclk_configure()
1936 apll = etdm_data->mclk_apll; in mtk_dai_etdm_mclk_configure()
1937 apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll); in mtk_dai_etdm_mclk_configure()
1941 /* select apll */ in mtk_dai_etdm_mclk_configure()
2151 int apll;
2163 apll = mt8195_afe_get_default_mclk_source_by_rate(freq); in mtk_dai_etdm_cal_mclk()
2164 apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll); in mtk_dai_etdm_cal_mclk()
2167 dev_info(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); in mtk_dai_etdm_cal_mclk()
2172 dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll); in mtk_dai_etdm_cal_mclk()
1917 int apll; mtk_dai_etdm_mclk_configure() local
2156 int apll; mtk_dai_etdm_cal_mclk() local
[all...]
/linux/arch/arm64/boot/dts/xilinx/
H A Dxlnx-zynqmp-clk.h14 #define APLL 2 macro

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