xref: /linux/Documentation/devicetree/bindings/clock/ti/ti,apll-clock.yaml (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/ti/ti,apll-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments APLL clock
8
9maintainers:
10  - Eduard Bostina <egbostina@gmail.com>
11
12allOf:
13  - $ref: /schemas/clock/clock.yaml#
14
15description:
16  This binding assumes a register-mapped APLL with usually two selectable
17  input clocks (reference clock and bypass clock), with analog phase locked
18  loop logic for multiplying the input clock to a desired output clock.
19  This clock also typically supports different operation modes (locked, low
20  power stop etc.) APLL mostly behaves like a subtype of a DPLL, although
21  a simplified one at that.
22
23properties:
24  compatible:
25    enum:
26      - ti,dra7-apll-clock
27      - ti,omap2-apll-clock
28
29  "#clock-cells":
30    const: 0
31
32  clocks:
33    minItems: 1
34    maxItems: 2
35    description: Link phandles of parent clocks (clk-ref and clk-bypass)
36
37  reg:
38    minItems: 2
39    maxItems: 3
40    description: |
41      Address and length of the register set for controlling the APLL.
42      It contains the information of registers in the following order:
43      "control" - contains the control register offset
44      "idlest" - contains the idlest register offset
45      "autoidle" - contains the autoidle register offset (OMAP2 only)
46
47  ti,clock-frequency:
48    $ref: /schemas/types.yaml#/definitions/uint32
49    description: static clock frequency for the clock (OMAP2 only)
50
51  ti,idlest-shift:
52    $ref: /schemas/types.yaml#/definitions/uint32
53    description: bit-shift for the idlest field (OMAP2 only)
54
55  ti,bit-shift:
56    $ref: /schemas/types.yaml#/definitions/uint32
57    description: bit-shift for enable and autoidle fields (OMAP2 only)
58
59required:
60  - compatible
61  - "#clock-cells"
62  - clocks
63  - reg
64
65unevaluatedProperties: false
66
67examples:
68  - |
69    bus {
70        #address-cells = <1>;
71        #size-cells = <0>;
72
73        clock@21c {
74            #clock-cells = <0>;
75            compatible = "ti,dra7-apll-clock";
76            clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
77            reg = <0x021c>, <0x0220>;
78        };
79
80        clock@500 {
81            #clock-cells = <0>;
82            compatible = "ti,omap2-apll-clock";
83            clocks = <&sys_ck>;
84            ti,bit-shift = <2>;
85            ti,idlest-shift = <8>;
86            ti,clock-frequency = <96000000>;
87            reg = <0x0500>, <0x0530>, <0x0520>;
88        };
89    };
90