/linux/tools/power/x86/intel-speed-select/ |
H A D | isst-core-mbox.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Intel Speed Select -- Enumerate and control features for Mailbox Interface 34 snprintf(level_str, sizeof(level_str), "level-%d", level); in mbox_get_trl_level_name() 66 if (id->cpu < 0) in mbox_is_punit_valid() 69 if (id->pkg < 0 || id->die < 0 || id->punit) in mbox_is_punit_valid() 75 static int _send_mmio_command(unsigned int cpu, unsigned int reg, int write, in _send_mmio_command() argument 84 debug_printf("mmio_cmd cpu:%d reg:%d write:%d\n", cpu, reg, write); in _send_mmio_command() 88 err(-1, "%s open failed", pathname); in _send_mmio_command() 91 io_regs.io_reg[0].logical_cpu = cpu; in _send_mmio_command() 101 if (ioctl(fd, cmd, &io_regs) == -1) { in _send_mmio_command() [all …]
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/linux/arch/mips/kernel/ |
H A D | smp-bmips.c | 20 #include <linux/cpu.h> 40 #include <asm/cpu-features.h> 53 static void bmips_set_reset_vec(int cpu, u32 val); 59 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ 63 static void bmips43xx_send_ipi_single(int cpu, unsigned int action); 64 static void bmips5000_send_ipi_single(int cpu, unsigned int action); 72 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) argument 73 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument 74 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument 75 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) argument [all …]
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/linux/tools/perf/util/ |
H A D | affinity.c | 1 // SPDX-License-Identifier: GPL-2.0 15 int sz = cpu__max_cpu().cpu + 8 - 1; in get_cpu_set_size() 22 return sz / 8; in get_cpu_set_size() 29 a->orig_cpus = bitmap_zalloc(cpu_set_size * 8); in affinity__setup() 30 if (!a->orig_cpus) in affinity__setup() 31 return -1; in affinity__setup() 32 sched_getaffinity(0, cpu_set_size, (cpu_set_t *)a->orig_cpus); in affinity__setup() 33 a->sched_cpus = bitmap_zalloc(cpu_set_size * 8); in affinity__setup() 34 if (!a->sched_cpus) { in affinity__setup() 35 zfree(&a->orig_cpus); in affinity__setup() [all …]
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/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5422-odroidhc1.dts | 1 // SPDX-License-Identifier: GPL-2.0 10 /dts-v1/; 11 #include <dt-bindings/leds/common.h> 12 #include "exynos5422-odroid-core.dtsi" 16 compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ 19 led-controller { 20 compatible = "pwm-leds"; 22 led-1 { 26 pwm-names = "pwm2"; 27 max-brightness = <255>; [all …]
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H A D | exynos5422-odroidxu3-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source 12 #include <dt-bindings/input/input.h> 13 #include "exynos5422-odroid-core.dtsi" 20 gpio-keys { 21 compatible = "gpio-keys"; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&power_key>; 25 power-key { 36 debounce-interval = <0>; [all …]
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/linux/arch/x86/kernel/ |
H A D | head_64.S | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 21 #include <asm/processor-flags.h> 25 #include <asm/nospec-branch.h> 33 * because we need identity-mapped pages. 41 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 66 * Note that on SMP the boot CPU uses the init data section until 67 * the per-CPU areas are set up. 89 * be done now, since this also includes setup of the SEV-SNP CPUID table, 97 /* Sanitize CPU configuration */ [all …]
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H A D | msr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* ----------------------------------------------------------------------- * 4 * Copyright 2000-2008 H. Peter Anvin - All Rights Reserved 7 * ----------------------------------------------------------------------- */ 13 * and then read/write in chunks of 8 bytes. A larger size means multiple 16 * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on 17 * an SMP box will direct the access to CPU %d. 33 #include <linux/cpu.h> 58 int cpu = iminor(file_inode(file)); in msr_read() local 62 if (count % 8) in msr_read() [all …]
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/linux/drivers/clk/mvebu/ |
H A D | dove.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 14 #include <linux/clk-provider.h> 18 #include "dove-divider.h" 23 * Dove PLL sample-at-reset configuration 25 * SAR0[8:5] : CPU frequency 29 * 8 = 800 MHz 39 * SAR0[11:9] : CPU to L2 Clock divider ratio 40 * 0 = (1/1) * CPU 41 * 2 = (1/2) * CPU [all …]
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H A D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Marvell MVEBU CPU clock handling. 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 13 #include <linux/clk-provider.h> 18 #include <linux/mvebu-pmsu.h> 23 #define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT 8 35 int cpu; member 54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate() 55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; in clk_cpu_recalc_rate() 65 div = req->best_parent_rate / req->rate; in clk_cpu_determine_rate() [all …]
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/linux/arch/alpha/kernel/ |
H A D | core_mcpcia.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Code common to all MCbus-PCI Adaptor core logic chipsets 27 * NOTE: Herein lie back-to-back mb instructions. They are magic. 33 * BIOS32-style PCI interface: 54 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 55 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 57 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 60 * 10:8 Function number 66 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 67 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ [all …]
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H A D | core_t2.c | 1 // SPDX-License-Identifier: GPL-2.0 37 * By default, we direct-map starting at 2GB, in order to allow the 38 * maximum size direct-map window (2GB) to match the maximum amount of 40 * floppy to DMA only via the scatter/gather window set up for 8MB 41 * ISA DMA, since the maximum ISA DMA address is 2GB-1. 43 * For now, this seems a reasonable trade-off: even though most SABLEs 62 * NOTE: Herein lie back-to-back mb instructions. They are magic. 68 * BIOS32-style PCI interface: 108 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 109 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ [all …]
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/linux/arch/arc/include/asm/ |
H A D | mmu_context.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 6 * -Refactored get_new_mmu_context( ) to only handle live-mm. 7 * retiring-mm handled in other hooks 10 * -Major rewrite of Core ASID allocation routine get_new_mmu_context 21 #include <asm-generic/mm_hooks.h> 25 * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on 26 * context-switch. 28 * ASID is managed per cpu, so task threads across CPUs can have different 32 * Each task is assigned unique ASID, with a simple round-robin allocator [all …]
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/linux/tools/power/x86/x86_energy_perf_policy/ |
H A D | x86_energy_perf_policy.8 | 1 .\" This page Copyright (C) 2010 - 2015 Len Brown <len.brown@intel.com> 3 .TH X86_ENERGY_PERF_POLICY 8 5 x86_energy_perf_policy \- Manage Energy vs. Performance Policy 10 .RB "scope: \-\-cpu\ cpu-list | \-\-pk [all...] |
/linux/arch/x86/include/asm/ |
H A D | segment.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 14 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \ 16 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \ 25 #define __BOOT_CS (GDT_ENTRY_BOOT_CS*8) 26 #define __BOOT_DS (GDT_ENTRY_BOOT_DS*8) 27 #define __BOOT_TSS (GDT_ENTRY_BOOT_TSS*8) 61 * The layout of the per-CPU GDT under Linux: 63 * 0 - null <=== cacheline #1 64 * 1 - reserved 65 * 2 - reserved [all …]
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H A D | cpufeatures.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 6 * Defines x86 CPU feature bits 8 #define NCAPINTS 22 /* N 32-bit words worth of info */ 9 #define NBUGINTS 2 /* N 32-bit bug flags */ 17 * please update the table in kernel/cpu/cpuid-deps.c as well. 20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ 26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */ 29 #define X86_FEATURE_CX8 ( 0*32+ 8) /* "cx8" CMPXCHG8 instruction */ 37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */ 46 #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ [all …]
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/linux/Documentation/translations/zh_CN/core-api/ |
H A D | workqueue.rst | 1 .. SPDX-License-Identifier: GPL-2.0 2 .. include:: ../disclaimer-zh_CN.rst 4 :Original: Documentation/core-api/workqueue.rst 109 每个与实际CPU绑定的worker-pool通过钩住调度器来实现并发管理。每当 139 参数 - ``@name`` , ``@flags`` 和 ``@max_active`` 。 148 --------- 202 -------------- 234 0 w0 starts and burns CPU 236 15 w0 wakes up and burns CPU 238 20 w1 starts and burns CPU [all …]
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/linux/tools/power/x86/intel_pstate_tracer/ |
H A D | intel_pstate_tracer.py | 2 # SPDX-License-Identifier: GPL-2.0-only 3 # -*- coding: utf-8 -*- 7 - If there is Linux trace file with pstate_sample events enabled, then 9 - If user has not specified a trace file as input via command line parameters, 16 python3-gnuplot 1.8 or higher 18 gnuplot-py, python-gnuplot or python3-gnuplot, gnuplot-nox, ... ) 20 HWP (Hardware P-States are disabled) 57 C_MPERF = 8 79 print(' ./%s_tracer.py [-c cpus] -t <trace_file> -n <test_name>'%driver_name) 81 …print(' ./%s_tracer.py [--cpu cpus] ---trace_file <trace_file> --name <test_name>'%driver_nam… [all …]
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/linux/arch/powerpc/platforms/powermac/ |
H A D | smp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 12 * code to detect this card though and disable SMP. --BenH. 17 * Support for DayStar quad CPU cards 18 * Copyright (C) XLR8, Inc. 1994-2000 32 #include <linux/cpu.h> 38 #include <asm/text-patching.h> 89 /* Daystar/XLR8 4-CPU card */ 99 #define PSURGE_QUAD_CKSTOP_RDBK 8 115 #define PSURGE_NONE -1 131 static inline void psurge_set_ipi(int cpu) in psurge_set_ipi() argument [all …]
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/linux/arch/powerpc/include/asm/ |
H A D | cputhreads.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 15 * as the CPU numbers are still allocated, just not brought online). 41 int cpu_core_index_of_thread(int cpu); 44 static inline int cpu_core_index_of_thread(int cpu) { return cpu; } in cpu_core_index_of_thread() argument 48 static inline int cpu_thread_in_core(int cpu) in cpu_thread_in_core() argument 50 return cpu & (threads_per_core - 1); in cpu_thread_in_core() 53 static inline int cpu_thread_in_subcore(int cpu) in cpu_thread_in_subcore() argument 55 return cpu & (threads_per_subcore - 1); in cpu_thread_in_subcore() 58 static inline int cpu_first_thread_sibling(int cpu) in cpu_first_thread_sibling() argument 60 return cpu & ~(threads_per_core - 1); in cpu_first_thread_sibling() [all …]
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/linux/net/netfilter/ |
H A D | nf_flow_table_procfs.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 int cpu; in nf_flow_table_cpu_seq_start() local 14 for (cpu = *pos - 1; cpu < nr_cpu_ids; ++cpu) { in nf_flow_table_cpu_seq_start() 15 if (!cpu_possible(cpu)) in nf_flow_table_cpu_seq_start() 17 *pos = cpu + 1; in nf_flow_table_cpu_seq_start() 18 return per_cpu_ptr(net->ft.stat, cpu); in nf_flow_table_cpu_seq_start() 27 int cpu; in nf_flow_table_cpu_seq_next() local 29 for (cpu = *pos; cpu < nr_cpu_ids; ++cpu) { in nf_flow_table_cpu_seq_next() 30 if (!cpu_possible(cpu)) in nf_flow_table_cpu_seq_next() 32 *pos = cpu + 1; in nf_flow_table_cpu_seq_next() [all …]
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/linux/tools/power/cpupower/debug/i386/ |
H A D | centrino-decode.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * (C) 2003 - 2004 Dominik Brodowski <linux@dominikbrodowski.de> 6 * linux/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c 9 * USAGE: simply run it to decode the current settings on CPU 0, 10 * or pass the CPU number as argument, or pass the MSR content 28 static int rdmsr(unsigned int cpu, unsigned int msr, in rdmsr() argument 34 int retval = -1; in rdmsr() 38 if (cpu > MCPU) in rdmsr() 41 sprintf(file, "/dev/cpu/%d/msr", cpu); in rdmsr() 47 if (lseek(fd, msr, SEEK_CUR) == -1) in rdmsr() [all …]
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/linux/tools/arch/x86/include/asm/ |
H A D | cpufeatures.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 6 * Defines x86 CPU feature bits 8 #define NCAPINTS 22 /* N 32-bit words worth of info */ 9 #define NBUGINTS 2 /* N 32-bit bug flags */ 17 * please update the table in kernel/cpu/cpuid-deps.c as well. 20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ 26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */ 29 #define X86_FEATURE_CX8 ( 0*32+ 8) /* "cx8" CMPXCHG8 instruction */ 37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */ 46 #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ [all …]
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/linux/arch/riscv/kernel/ |
H A D | traps_misaligned.c | 1 // SPDX-License-Identifier: GPL-2.0-only 16 #include <asm/entry-common.h> 35 regs->status |= SR_FS_DIRTY; in set_f32_rd() 53 regs->status |= SR_FS_DIRTY; in set_f64_rd() 68 regs->status |= SR_FS_DIRTY; in get_f64_rs() 83 regs->status |= SR_FS_DIRTY; in get_f64_rs() 99 regs->status |= SR_FS_DIRTY; in get_f32_rs() 154 return -EFAULT; in get_insn() 166 return -EFAULT; in get_insn() 172 return -EFAULT; in get_insn() [all …]
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/linux/drivers/media/platform/verisilicon/ |
H A D | hantro_vp8.c | 1 // SPDX-License-Identifier: GPL-2.0 30 u8 prob_coeffs[4][8][3][V4L2_VP8_COEFF_PROB_CNT]; 35 * filter taps taken to 7-bit precision, 36 * reference RFC6386#Page-16, filters[8][6] 38 const u32 hantro_vp8_dec_mc_filter[8][6] = { 40 { 0, -6, 123, 12, -1, 0 }, 41 { 2, -11, 108, 36, -8, 1 }, 42 { 0, -9, 93, 50, -6, 0 }, 43 { 3, -16, 77, 77, -16, 3 }, 44 { 0, -6, 50, 93, -9, 0 }, [all …]
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/linux/drivers/leds/trigger/ |
H A D | ledtrig-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * ledtrig-cpu.c - LED trigger based on CPU activity 5 * This LED trigger will be registered for first 8 CPUs and named 6 * as cpu0..cpu7. There's additional trigger called cpu that 7 * is on when any CPU is active. 10 * with additional sysfs file selecting which CPU to watch. 15 * An API named ledtrig_cpu is exported for any user, who want to add CPU 19 * Copyright 2011 - 2012 Bryan Wu <bryan.wu@canonical.com> 28 #include <linux/cpu.h> 31 #define MAX_NAME_LEN 8 [all …]
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