Lines Matching +full:8 +full:- +full:cpu
1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
14 #include <linux/clk-provider.h>
18 #include "dove-divider.h"
23 * Dove PLL sample-at-reset configuration
25 * SAR0[8:5] : CPU frequency
29 * 8 = 800 MHz
39 * SAR0[11:9] : CPU to L2 Clock divider ratio
40 * 0 = (1/1) * CPU
41 * 2 = (1/2) * CPU
42 * 4 = (1/3) * CPU
43 * 6 = (1/4) * CPU
46 * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
47 * 0 = (1/1) * CPU
48 * 2 = (1/2) * CPU
49 * 3 = (2/5) * CPU
50 * 4 = (1/3) * CPU
51 * 6 = (1/4) * CPU
52 * 8 = (1/5) * CPU
53 * 10 = (1/6) * CPU
54 * 12 = (1/7) * CPU
55 * 14 = (1/8) * CPU
56 * 15 = (1/10) * CPU
113 static const int dove_cpu_l2_ratios[8][2] __initconst = {
122 { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
167 { "sdio0", NULL, 8, 0 },
185 of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock"); in dove_clk_init()
187 of_find_compatible_node(NULL, NULL, "marvell,dove-divider-clock"); in dove_clk_init()
201 CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);